AN 900: Intel® Arria 10 DisplayPort 8K RX-only Design

ID 683799
Date 7/02/2021
Public

1.3. Top Level Interface Signals

The tables list the signals for the RX-only design example.
Table 5.  On-board Oscillator Signal
Signal Direction Width Description
refclk1_p

Input

1

100 MHz clock source used as IOPLL reference clock and Avalon® memory-mapped management clock

Table 6.  User Push Buttons and LEDs
Signal Direction Width Description
cpu_resetn

Input

1

Global reset

user_pb Input 3 MSA prints out at user_pb[0]
user_led_g Output 8 User LED (data rate information)
Table 7.  DisplayPort FMC Daughter Card Pins on FMC Port A
Signal Direction Width Description
fmca_gbtclk_m2c_p

Input

2

135 MHz dedicated transceiver reference clock

fmca_dp_m2c_p

Input

4

DisplayPort RX serial data

fmca_la_rx_p_6

Output

1
DisplayPort RX HPD
  • 1 = HPD asserted
  • 0 = HPD deasserted
fmca_la_tx_n_9

Input

1

DisplayPort RX Aux In

fmca_la_rx_n_6

Output

1

DisplayPort RX Aux Out

fmca_la_tx_p_9 Output 1 DisplayPort RX Aux OE
fmca_la_rx_n_8

Input

1

RX power detect (inverted)

fmca_la_tx_p_10

Input

1

RX cable detect

Table 8.  FMC Onboard Retimer Reconfiguration Interface Signals
Signal Direction Width Description
Bitec FMC Revision 10 Bitec FMC Revision 11
fmca_la_tx_p_0

Inout

1 PS8460_SDA MCDP6000_SDA
fmca_la_tx_n_0

Inout

1

PS8460_SCL

MCDP6000_SDL

fmca_la_rx_p_0

Output

1

PS8460_EQ0

Unused
fmca_la_rx_n_0

Output

1

PS8460_EQ1

Unused
fmca_la_tx_p_1

Output

1

PS8460_PDN

Unused
fmca_la_tx_n_1

Output

1

PS8460_CFG0

Unused
fmca_la_tx_p_2

Output

1

PS8460_CFG1

Unused
fmca_la_tx_n_2

Output

1

PS8460_CFG2

Unused

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