AN 900: Intel® Arria 10 DisplayPort 8K RX-only Design

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ID 683799
Date 7/02/2021
Public
Document Table of Contents
Document Table of Contents x
1. Intel® Arria® 10 DisplayPort 8K RX-only Design
1. Intel® Arria® 10 DisplayPort 8K RX-only Design x
1.1. Design Components 1.2. Clocking Scheme 1.3. Top Level Interface Signals 1.4. Quick Start Guide 1.5. Creating the RX-only Design 1.6. Document Revision History for AN 900: Intel® Arria® 10 DisplayPort 8K RX-only Design
1.4. Quick Start Guide x
1.4.1. Hardware and Software Requirements 1.4.2. Directory Structure 1.4.3. Compiling the Design 1.4.4. Running the Design on Hardware 1.4.5. Design Debug Features
1.4.3. Compiling the Design x
1.4.3.1. Regenerating and Downloading ELF File
1.4.5. Design Debug Features x
1.4.5.1. Main Stream Attribute (MSA) Information 1.4.5.2. Auxiliary Channel Traffic Monitor 1.4.5.3. Signal Tap Logic Analyzer 1.4.5.4. Onboard User LED Functions
1.5. Creating the RX-only Design x
1.5.1. Generating the Design 1.5.2. Removing Irrelevant Blocks 1.5.3. Making a Direct Connection to the RX Transceiver Block 1.5.4. Selecting the Bitec FMC Daughter Card Revision 1.5.5. Modifying the Software
1.5.2. Removing Irrelevant Blocks x
1.5.2.1. Removing Irrelevant Block in Top Level Example Design a10_dp_demo.v File 1.5.2.2. Removing Irrelevant Block in Platform Designer
1. Intel® Arria® 10 DisplayPort 8K RX-only Design

1.3. Top Level Interface Signals

The tables list the signals for the RX-only design example.
Table 5.  On-board Oscillator Signal
Signal Direction Width Description
refclk1_p

Input

 1

100 MHz clock source used as IOPLL reference clock and Avalon® memory-mapped management clock

Table 6.  User Push Buttons and LEDs
Signal Direction Width Description
cpu_resetn

Input

 1

Global reset
user_pb Input 3 MSA prints out at user_pb[0]
user_led_g Output 8 User LED (data rate information)
Table 7.  DisplayPort FMC Daughter Card Pins on FMC Port A
Signal Direction Width Description
fmca_gbtclk_m2c_p

Input

2

135 MHz dedicated transceiver reference clock

fmca_dp_m2c_p

Input

 4

DisplayPort RX serial data
fmca_la_rx_p_6

Output

 1
DisplayPort RX HPD
  • 1 = HPD asserted
  • 0 = HPD deasserted
fmca_la_tx_n_9

Input

 1

DisplayPort RX Aux In
fmca_la_rx_n_6

Output

 1

DisplayPort RX Aux Out
fmca_la_tx_p_9 Output 1 DisplayPort RX Aux OE
fmca_la_rx_n_8

Input

 1

RX power detect (inverted)
fmca_la_tx_p_10

Input

 1

RX cable detect
Table 8.  FMC Onboard Retimer Reconfiguration Interface Signals
Signal Direction Width Description
Bitec FMC Revision 10 Bitec FMC Revision 11
fmca_la_tx_p_0

Inout

 1 PS8460_SDA MCDP6000_SDA
fmca_la_tx_n_0

Inout

 1

PS8460_SCL

MCDP6000_SDL
fmca_la_rx_p_0

Output

 1

PS8460_EQ0

 Unused
fmca_la_rx_n_0

Output

 1

PS8460_EQ1

 Unused
fmca_la_tx_p_1

Output

 1

PS8460_PDN

 Unused
fmca_la_tx_n_1

Output

 1

PS8460_CFG0

 Unused
fmca_la_tx_p_2

Output

 1

PS8460_CFG1

 Unused
fmca_la_tx_n_2

Output

 1

PS8460_CFG2

 Unused
Level Two Title