About the 8K DisplayPort Video Format Conversion Design Example
The design is highly software and hardware configurable, enabling rapid system configuration and redesign. The design targets Intel® Arria® 10 devices and uses the latest 8K ready Intel® FPGA IP from the Video and Image Processing Suite in Intel® Quartus® Prime v19.2.
About DisplayPort Intel® FPGA IP
To create Intel® Arria® 10 FPGA designs with DisplayPort interfaces, instantiate the DisplayPort Intel® FPGA IP. However, this DisplayPort IP only implements the protocol encode or decode for DisplayPort. It does not include the transceivers, PLLs, or transceiver reconfiguration functionality required to implement the high-speed serial component of the interface. Intel provides separate transceiver, PLL, and reconfiguration IP components. Selecting, parameterizing, and connecting these components to create a fully compliant DisplayPort receiver or transmitter interface requires specialist knowledge.
Intel provides this design for those who are not transceiver experts. The parameter editor GUI for the DisplayPort IP allows you to build the design.
You create an instance of the DisplayPort IP (which may be receiver only, transmitter only or combined receiver and transmitter) in either Platform Designer or the IP Catalog. When you parameterize the DisplayPort IP instance, you can select to generate an example design for that particular configuration. The combined receiver and transmitter design is a simple passthrough, where the output from the receiver feeds directly in to the transmitter. A fixed-passthrough design creates a fully functional receiver PHY, transmitter PHY, and reconfiguration blocks that implement all the transceiver and PLL logic. You can either directly copy the relevant sections of the design, or use the design as a reference. The design generates a DisplayPort Intel® Arria® 10 FPGA IP Design Example and then adds many of the files generated directly into the compile list used by the Intel® Quartus® Prime project. These include:
- Files to create parameterized IP instances for transceivers, PLLs and reconfig blocks.
- Verilog HDL files to connect these IPs into the higher level receiver PHY, transmitter PHY, and Transceiver Reconfiguration Arbiter blocks
- Synopsys design constraint (SDC) files to set the relevant timing constraints.