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A.1. Modify the Intel® Stratix® 10 SX SoC Development Kit to use a battery for the BBRAM
A.2. Modify the Intel® Stratix® 10 SX SoC Development Kit HPS DDR4 memory width and ECC configuration using the Golden Hardware Reference Design project
A.3. Safety and Regulatory Information
A.4. Compliance Information
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1. Overview
This document describes the features of the Intel® Stratix® 10 SoC development kit, including detailed pin-out and component reference information required to create custom FPGA designs that interface with all components of the board.
This development board comes in two different versions as shown in the table below.
Development Kit Version | Ordering Code | Device Part Number |
---|---|---|
Intel Stratix 10 SX SoC L-Tile | DK-SOC-1SSX-L-A DK-SOC-1SSX-L-D |
1SX280LU2F50E1VG |
Intel Stratix 10 SX SoC H-Tile | DK-SOC-1SSX-H-A | 1SX280HU2F50E1VGAS |
Figure 1. Development Kit Picture

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