Intel® Stratix® 10 SX SoC Development Kit User Guide

ID 683303
Date 6/02/2023
Document Table of Contents

A.1. Modify the Intel® Stratix® 10 SX SoC Development Kit to use a battery for the BBRAM

The Intel® Stratix® 10 device contains a Battery Backed-up RAM (BBRAM) that is used by the Secure Device Manager. The BBRAM is powered by a special pin on the FPGA named VCCBAT. On the Intel® Stratix® 10 SX SoC Development Kit, this pin is connected to the main power, and the contents of the BBRAM are lost when the board is powered down. This section describes how to modify the board to accommodate a battery so the BBRAM contents can be preserved when the board loses power.

The modification to the board involves moving a zero-ohm surface mount resistor from one location to another, and then adding a suitable battery power source to a header.

The following schematic diagram shows the default board layout.

By default, the VCCBAT pin is powered by the VCCPT power rail through the zero ohm resistor R720. Removing R720 and inserting it in the unpopulated R721 position will cause the power for VCCBAT to come from J27, which is a simple 2 pin 0.1” spaced header. Power can be provided to J27 using a battery with a voltage of 1.2 – 1.8 volts.