Stratix® 10 SX SoC Development Kit User Guide

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ID 683303
Date 6/06/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Kit Setup 4. Development Kit Components 5. Board Test System A. Additional Information B. Document Revision History for the Stratix® 10 10 SX SoC Development Kit User Guide
1. Overview x
1.1. General Development Kit Description 1.2. Recommended Operating Conditions 1.3. Handling the Development Kit
2. Getting Started x
2.1. Installing Quartus® Prime Software 2.2. Installing the Intel® FPGA Download Cable 2.3. Installing the Intel SoC Embedded Development Suite (EDS) 2.4. Installing the Stratix® 10 SX SoC Development Kit Package
3. Development Kit Setup x
3.1. Inspect the Development Kit 3.2. Default Setup of the Development Kit 3.3. MAX® 10 System Controller Updates
4. Development Kit Components x
4.1. Development Kit Feature Summary 4.2. Board Components 4.3. Stratix® 10 SoC Device Overview 4.4. MAX® 10 System Controller Overview 4.5. FPGA Configuration 4.6. General User Input/Output 4.7. Connectors and Interfaces 4.8. Daughter Cards 4.9. System Memory 4.10. System Power
4.7. Connectors and Interfaces x
4.7.1. PCIe* Slot 4.7.2. ZQSFP+ 4.7.3. SFP+ 4.7.4. HDMI 4.7.5. SDI Port 4.7.6. MXP 4.7.7. Intel® FPGA Download Cable Direct Port (Debug Port) 4.7.8. FMC+ A/B Slot 4.7.9. FMC+ A/B LVDS Interfaces (LPC Pins) 4.7.10. LMK05028 Jitter Attenuator 4.7.11. FPGA-IOMAX10 Interface
4.8. Daughter Cards x
4.8.1. HPS IO-48 OOBE Daughter Card 4.8.2. HPS IO-48 NAND Flash Daughter Card 4.8.3. HPS Boot Flash Card
4.8.3. HPS Boot Flash Card x
4.8.3.1. Boot QSPI Flash Daughter Card 4.8.3.2. Boot MicroSD Daughter Card 4.8.3.3. Boot eMMC Daughter Card
4.9. System Memory x
4.9.1. FPGA Memory (DDR4 SO-DIMM) 4.9.2. HPS Memory (External 4 GB HILO x72 DDR4) 4.9.3. HPS I2C Interface
4.10. System Power x
4.10.1. Power Supply Options 4.10.2. Power Sequence 4.10.3. Power Distribution Network
5. Board Test System x
5.1. Preparing the Board 5.2. Running the BTS 5.3. Using the BTS
5.3. Using the BTS x
5.3.1. The Configure Menu 5.3.2. The GPIO Tab 5.3.3. The QSFP/SFP Tab 5.3.4. The PCIE Tab 5.3.5. The MXP Tab 5.3.6. The FMCA Tab 5.3.7. The FMCB Tab 5.3.8. The DDR4 Tab 5.3.9. Power Monitor 5.3.10. The Clock Control
A. Additional Information x
A.1. Modify the Stratix® 10 SX SoC Development Kit to use a battery for the BBRAM A.2. Modify the Stratix® 10 SX SoC Development Kit HPS DDR4 memory width and ECC configuration using the Golden Hardware Reference Design project A.3. Safety and Regulatory Information A.4. Compliance Information
A.3. Safety and Regulatory Information x
A.3.1. Safety Warnings A.3.2. Safety Cautions
A.4. Compliance Information x
A.4.1. Compliance and Conformity Statements
1. Overview
2. Getting Started
3. Development Kit Setup
4. Development Kit Components
5. Board Test System
A. Additional Information
B. Document Revision History for the Stratix® 10 10 SX SoC Development Kit User Guide

4.9.1. FPGA Memory (DDR4 SO-DIMM)

The 72-bit memory interface connected to the SO-DIMM card is assigned to four I/O banks (3I, 3J, 3K and 3L). The reference clock of the DDR4 port is the 133.33 MHz clock generated by Silicon Lab Si5338. The SODIMM memory part number is MTA18ASF2G72Hz. Its I2C EEPROM Address is 0b1010101. Its Temp Sensor Address is 0b0011101.

Table 45.  SO-DIMM FPGA Pin Map
Pin Name Schematic Signal Name Description
PIN_V21 SL_DQB3 DDR4 DQ
PIN_V22 SL_DQB1 DDR4 DQ
PIN_T21 SL_DQB7 DDR4 DQ
PIN_R21 SL_DQB6 DDR4 DQ
PIN_V23 SL_DQB4 DDR4 DQ
PIN_V24 SL_DQB5 DDR4 DQ
PIN_U20 SL_DQSN0 DDR4 DQSN
PIN_T20 SL_DQSP0 DDR4 DQSP
PIN_R22 SL_DQB0 DDR4 DQ
PIN_T22 SL_DQB2 DDR4 DQ
PIN_U23 SL_DM0 DDR4 DM
PIN_E11 SL_DQB37 DDR4 DQ
PIN_F11 SL_DQB33 DDR4 DQ
PIN_G10 SL_DQB39 DDR4 DQ
PIN_H10 SL_DQB35 DDR4 DQ
PIN_D10 SL_DQB36 DDR4 DQ
PIN_D11 SL_DQB32 DDR4 DQ
PIN_G12 SL_DQSN4 DDR4 DQSN
PIN_H12 SL_DQSP4 DDR4 DQSP
PIN_F10 SL_DQB34 DDR4 DQ
PIN_E10 SL_DQB38 DDR4 DQ
PIN_F12 SL_DM4 DDR4 DM
PIN_J11 SL_DQB56 DDR4 DQ
PIN_H11 SL_DQB61 DDR4 DQ
PIN_K11 SL_DQB58 DDR4 DQ
PIN_K12 SL_DQB59 DDR4 DQ
PIN_K10 SL_DQB63 DDR4 DQ
PIN_J10 SL_DQB62 DDR4 DQ
PIN_M12 SL_DQSN7 DDR4 DQSN
PIN_L12 SL_DQSP7 DDR4 DQSP
PIN_L10 SL_DQB60 DDR4 DQ
PIN_L11 SL_DQB57 DDR4 DQ
PIN_K13 SL_DM7 DDR4 DM
PIN_N13 SL_DQB46 DDR4 DQ
PIN_P14 SL_DQB47 DDR4 DQ
PIN_M13 SL_DQB41 DDR4 DQ
PIN_M14 SL_DQB44 DDR4 DQ
PIN_P15 SL_DQB42 DDR4 DQ
PIN_P16 SL_DQB40 DDR4 DQ
PIN_P13 SL_DQSN5 DDR4 DQSN
PIN_P12 SL_DQSP5 DDR4 DQSP
PIN_R16 SL_DQB45 DDR4 DQ
PIN_R17 SL_DQB43 DDR4 DQ
PIN_R14 SL_DM5 DDR4 DM
PIN_T19 SL_DQB14 DDR4 DQ
PIN_U19 SL_DQB9 DDR4 DQ
PIN_R18 SL_DQB10 DDR4 DQ
PIN_R19 SL_DQB11 DDR4 DQ
PIN_W18 SL_DQB12 DDR4 DQ
PIN_V17 SL_DQB13 DDR4 DQ
PIN_T17 SL_DQSN1 DDR4 DQSN
PIN_U17 SL_DQSP1 DDR4 DQSP
PIN_U18 SL_DQB15 DDR4 DQ
PIN_V18 SL_DQB8 DDR4 DQ
PIN_T16 SL_DM1 DDR4 DM
PIN_M15 SL_CK1N DDR4 Bank 1 ClockN
PIN_N15 SL_CK1P DDR4 Bank 1 ClockP
PIN_K16 SL_ALERTN DDR4 ALERTn
PIN_L16 SL_EVENTN DDR4 SO-DIMM Eventn
PIN_M18 SL_C1N DDR4 Bank 1 C1
PIN_M17 SL_C0N DDR4 Bank 0 C0
PIN_J14 SL_BG0 DDR4 BG0
PIN_K14 SL_BA1 DDR4 BA1
PIN_H17 SL_BA0 DDR4 BA0
PIN_F15 SL_RASN DDR4 RASN
PIN_G15 SL_CASN DDR4 CASN
PIN_J15 SL_WEN DDR4 WEN
PIN_H15 SL_A13 DDR4 A13
PIN_L14 SL_A12 DDR4 A12
PIN_H16 CLK_EMI_1N DDR4 EMIF Reference Clock N
PIN_J16 CLK_EMI_1P DDR4 EMIF Reference Clock P
PIN_F16 SL_A11 DDR4 A11
PIN_E16 SL_A10 DDR4 A10
PIN_D15 SL_A9 DDR4 A9
PIN_C15 SL_A8 DDR4 A8
PIN_B15 SL_A7 DDR4 A7
PIN_A16 SL_A6 DDR4 A6
PIN_B13 SL_A5 DDR4 A5
PIN_B14 SL_A4 DDR4 A4
PIN_A15 SL_A3 DDR4 A3
PIN_A14 SL_A2 DDR4 A2
PIN_D16 SL_A1 DDR4 A1
PIN_C16 SL_A0 DDR4 A0
PIN_A12 SL_PARITY DDR4 Parity
PIN_B12 SL_CS1N DDR4 BANK 1 CSN
PIN_D14 SL_CK0N DDR4 BANK 0 Clock N
PIN_E14 SL_CK0P DDR4 BANK 0 Clock P
PIN_C12 SL_CKE1 DDR4 BANK 1 CKE
PIN_C13 SL_CKE0 DDR4 BANK 0 CKE
PIN_F14 SL_ODT1N DDR4 BANK 1 ODTN
PIN_G14 SL_ODT0N DDR4 BANK 0 ODTN
PIN_D13 SL_ACTN DDR4 ACTn
PIN_E13 SL_CS0N DDR4 CS0n
PIN_H13 SL_RESETN DDR4 SO-DIMM RESETN
PIN_G13 SL_BG1 DDR4 BG1
PIN_B20 SL_DQB28 DDR4 DQ
PIN_A19 SL_DQB26 DDR4 DQ
PIN_B17 SL_DQB27 DDR4 DQ
PIN_A17 SL_DQB31 DDR4 DQ
PIN_A21 SL_DQB30 DDR4 DQ
PIN_A20 SL_DQB24 DDR4 DQ
PIN_C18 SL_DQSN3 DDR4 DQSN
PIN_C17 SL_DQSP3 DDR4 DQSP
PIN_B22 SL_DQB29 DDR4 DQ
PIN_A22 SL_DQB25 DDR4 DQ
PIN_B19 SL_DM3 DDR4 DM
PIN_E17 SL_DQB23 DDR4 DQ
PIN_F17 SL_DQB19 DDR4 DQ
PIN_D18 SL_DQB20 DDR4 DQ
PIN_E18 SL_DQB18 DDR4 DQ
PIN_D19 SL_DQB16 DDR4 DQ
PIN_E19 SL_DQB22 DDR4 DQ
PIN_C20 SL_DQSN2 DDR4 DQSN
PIN_D20 SL_DQSP2 DDR4 DQSP
PIN_D21 SL_DQB17 DDR4 DQ
PIN_E21 SL_DQB21 DDR4 DQ
PIN_C21 SL_DM2 DDR4 DM
PIN_J19 SL_DQB54 DDR4 DQ
PIN_J20 SL_DQB50 DDR4 DQ
PIN_F19 SL_DQB52 DDR4 DQ
PIN_G19 SL_DQB49 DDR4 DQ
PIN_K18 SL_DQB48 DDR4 DQ
PIN_J18 SL_DQB53 DDR4 DQ
PIN_F21 SL_DQSN6 DDR4 DQSN
PIN_F20 SL_DQSP6 DDR4 DQSP
PIN_H18 SL_DQB55 DDR4 DQ
PIN_G18 SL_DQB51 DDR4 DQ
PIN_H20 SL_DM6 DDR4 DM
PIN_H21 SL_DQB69 DDR4 DQ
PIN_J21 SL_DQB68 DDR4 DQ
PIN_L19 SL_DQB70 DDR4 DQ
PIN_K19 SL_DQB64 DDR4 DQ
PIN_L21 SL_DQB71 DDR4 DQ
PIN_K21 SL_DQB65 DDR4 DQ
PIN_L20 SL_DQSN8 DDR4 DQSN
PIN_M20 SL_DQSP8 DDR4 DQSP
PIN_N21 SL_DQB66 DDR4 DQ
PIN_P21 SL_DQB67 DDR4 DQ
PIN_N20 SL_DM8 DDR4 DM
Level Two Title