Intel® Stratix® 10 SX SoC Development Kit User Guide

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ID 683303
Date 6/02/2023
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Kit Setup 4. Development Kit Components 5. Board Test System A. Additional Information B. Revision History
1. Overview x
1.1. General Development Kit Description 1.2. Recommended Operating Conditions 1.3. Handling the Development Kit
2. Getting Started x
2.1. Installing Quartus Prime Software 2.2. Installing the Intel® FPGA Download Cable 2.3. Installing the Intel SoC Embedded Development Suite (EDS) 2.4. Installing the Intel® Stratix® 10 SX SoC Development Kit Package
3. Development Kit Setup x
3.1. Inspect the Development Kit 3.2. Default Setup of the Development Kit 3.3. Intel® MAX® 10 System Controller Updates
4. Development Kit Components x
4.1. Development Kit Feature Summary 4.2. Board Components 4.3. Intel® Stratix® 10 SoC Device Overview 4.4. Intel® MAX® 10 System Controller Overview 4.5. FPGA Configuration 4.6. General User Input/Output 4.7. Connectors and Interfaces 4.8. Daughter Cards 4.9. System Memory 4.10. System Power
4.7. Connectors and Interfaces x
4.7.1. PCIe* Slot 4.7.2. ZQSFP+ 4.7.3. SFP+ 4.7.4. HDMI 4.7.5. SDI Port 4.7.6. MXP 4.7.7. Intel® FPGA Download Cable Direct Port (Debug Port) 4.7.8. FMC+ A/B Slot 4.7.9. FMC+ A/B LVDS Interfaces (LPC Pins) 4.7.10. LMK05028 Jitter Attenuator 4.7.11. FPGA-IOMAX10 Interface
4.8. Daughter Cards x
4.8.1. HPS IO-48 OOBE Daughter Card 4.8.2. HPS IO-48 NAND Flash Daughter Card 4.8.3. HPS Boot Flash Card
4.8.3. HPS Boot Flash Card x
4.8.3.1. Boot QSPI Flash Daughter Card 4.8.3.2. Boot MicroSD Daughter Card 4.8.3.3. Boot eMMC Daughter Card
4.9. System Memory x
4.9.1. FPGA Memory (DDR4 SO-DIMM) 4.9.2. HPS Memory (External 4 GB HILO x72 DDR4 ) 4.9.3. HPS I2C Interface
4.10. System Power x
4.10.1. Power Supply Options 4.10.2. Power Sequence 4.10.3. Power Distribution Network
5. Board Test System x
5.1. Preparing the Board 5.2. Running the BTS 5.3. Using the BTS
5.3. Using the BTS x
5.3.1. The Configure Menu 5.3.2. The GPIO Tab 5.3.3. The QSFP/SFP Tab 5.3.4. The PCIE Tab 5.3.5. The MXP Tab 5.3.6. The FMCA Tab 5.3.7. The FMCB Tab 5.3.8. The DDR4 Tab 5.3.9. Power Monitor 5.3.10. The Clock Control
A. Additional Information x
A.1. Modify the Intel® Stratix® 10 SX SoC Development Kit to use a battery for the BBRAM A.2. Modify the Intel® Stratix® 10 SX SoC Development Kit HPS DDR4 memory width and ECC configuration using the Golden Hardware Reference Design project A.3. Safety and Regulatory Information A.4. Compliance Information
A.3. Safety and Regulatory Information x
A.3.1. Safety Warnings A.3.2. Safety Cautions
A.4. Compliance Information x
A.4.1. Compliance and Conformity Statements
B. Revision History x
B.1. Revision History
1. Overview
2. Getting Started
3. Development Kit Setup
4. Development Kit Components
5. Board Test System
A. Additional Information
B. Revision History

4.7.1. PCIe* Slot

The PCIe* root port is a PCIe* Gen3 x16 port. This port is assigned to 4K, 4L and 4M Banks. The transceiver I/O bank power is connected to 1.8 V.

PCIE_PRSNT2n, PCIE_PERSTn and PCIE_WAKE_N 3V3 signals are mapped to the dedicated transceiver I/O bank (IO4) in the Intel® MAX® 10. The system performance of the PCIe* root port should meet the PCIe* 3.0 specifications.

Table 13.  PCIE Root Port FPGA Pin Map
Pin Name Schematic Signal Name Direction Description
PIN_V12 PCIE_REFCLK_QR0_P Input REFCLK_GXBR4K_CHTP
PIN_V13 PCIE_REFCLK_QR0_N Input REFCLK_GXBR4K_CHTN
PIN_L4 PCIE_TX_N15 Output GXBR4M_TX_CH3N
PIN_L3 PCIE_TX_P15 Output GXBR4M_TX_CH3P
PIN_H6 PCIE_RX_N15 Input GXBR4M_RX_CH3N
PIN_H5 PCIE_RX_P15 Input GXBR4M_RX_CH3P
PIN_K2 PCIE_TX_N14 Output GXBR4M_TX_CH2N
PIN_K1 PCIE_TX_P14 Output GXBR4M_TX_CH2P
PIN_L8 PCIE_RX_N14 Input GXBR4M_RX_CH2N
PIN_L7 PCIE_RX_P14 Input GXBR4M_RX_CH2P
PIN_N4 PCIE_TX_N13 Output GXBR4M_TX_CH1N
PIN_N3 PCIE_TX_P13 Output GXBR4M_TX_CH1P
PIN_K6 PCIE_RX_N13 Input GXBR4M_RX_CH1N
PIN_K5 PCIE_RX_P13 Input GXBR4M_RX_CH1P
PIN_M2 PCIE_TX_N12 Output GXBR4M_TX_CH0N
PIN_M1 PCIE_TX_P12 Output GXBR4M_TX_CH0P
PIN_N8 PCIE_RX_N12 Input GXBR4M_RX_CH0N
PIN_N7 PCIE_RX_P12 Input GXBR4M_RX_CH0P
PIN_R4 PCIE_TX_N11 Output GXBR4L_TX_CH5N
PIN_R3 PCIE_TX_P11 Output GXBR4L_TX_CH5P
PIN_M6 PCIE_RX_N11 Input GXBR4L_RX_CH5N
PIN_M5 PCIE_RX_P11 Input GXBR4L_RX_CH5P
PIN_P2 PCIE_TX_N10 Output GXBR4L_TX_CH4N
PIN_P1 PCIE_TX_P10 Output GXBR4L_TX_CH4P
PIN_R8 PCIE_RX_N10 Input GXBR4L_RX_CH4N
PIN_R7 PCIE_RX_P10 Input GXBR4L_RX_CH4P
PIN_T2 PCIE_TX_N9 Output GXBR4L_TX_CH3N
PIN_T1 PCIE_TX_P9 Output GXBR4L_TX_CH3P
PIN_P6 PCIE_RX_N9 Input GXBR4L_RX_CH3N
PIN_P5 PCIE_RX_P9 Input GXBR4L_RX_CH3P
PIN_U4 PCIE_TX_N8 Output GXBR4L_TX_CH2N
PIN_U3 PCIE_TX_P8 Output GXBR4L_TX_CH2P
PIN_T6 PCIE_RX_N8 Input GXBR4L_RX_CH2N
PIN_T5 PCIE_RX_P8 Input GXBR4L_RX_CH2P
PIN_V2 PCIE_TX_N7 Output GXBR4L_TX_CH1N
PIN_V1 PCIE_TX_P7 Output GXBR4L_TX_CH1P
PIN_U8 PCIE_RX_N7 Input GXBR4L_RX_CH1N
PIN_U7 PCIE_RX_P7 Input GXBR4L_RX_CH1P
PIN_Y2 PCIE_TX_N6 Output GXBR4L_TX_CH0N
PIN_Y1 PCIE_TX_P6 Output GXBR4L_TX_CH0P
PIN_V6 PCIE_RX_N6 Input GXBR4L_RX_CH0N
PIN_V5 PCIE_RX_P6 Input GXBR4L_RX_CH0P
PIN_W4 PCIE_TX_N5 Output GXBR4K_TX_CH5N
PIN_W3 PCIE_TX_P5 Output GXBR4K_TX_CH5P
PIN_Y6 PCIE_RX_N5 Input GXBR4K_RX_CH5N
PIN_Y5 PCIE_RX_P5 Input GXBR4K_RX_CH5P
PIN_AB2 PCIE_TX_N4 Output GXBR4K_TX_CH4N
PIN_AB1 PCIE_TX_P4 Output GXBR4K_TX_CH4P
PIN_W8 PCIE_RX_N4 Input GXBR4K_RX_CH4N
PIN_W7 PCIE_RX_P4 Input GXBR4K_RX_CH4P
PIN_AA4 PCIE_TX_N3 Output GXBR4K_TX_CH3N
PIN_AA3 PCIE_TX_P3 Output GXBR4K_TX_CH3P
PIN_AB6 PCIE_RX_N3 Input GXBR4K_RX_CH3N
PIN_AB5 PCIE_RX_P3 Input GXBR4K_RX_CH3P
PIN_AD2 PCIE_TX_N2 Output GXBR4K_TX_CH2N
PIN_AD1 PCIE_TX_P2 Output GXBR4K_TX_CH2P
PIN_AA8 PCIE_RX_N2 Input GXBR4K_RX_CH2N
PIN_AA7 PCIE_RX_P2 Input GXBR4K_RX_CH2P
PIN_AC4 PCIE_TX_N1 Output GXBR4K_TX_CH1N
PIN_AC3 PCIE_TX_P1 Output GXBR4K_TX_CH1P
PIN_AD6 PCIE_RX_N1 Input GXBR4K_RX_CH1N
PIN_AD5 PCIE_RX_P1 Input GXBR4K_RX_CH1P
PIN_AE4 PCIE_TX_N0 Output GXBR4K_TX_CH0N
PIN_AE3 PCIE_TX_P0 Output GXBR4K_TX_CH0P
PIN_AC8 PCIE_RX_N0 Input GXBR4K_RX_CH0N
PIN_AC7 PCIE_RX_P0 Input GXBR4K_RX_CH0P
Level Two Title