Stratix® 10 SX SoC Development Kit User Guide

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ID 683303
Date 6/06/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Kit Setup 4. Development Kit Components 5. Board Test System A. Additional Information B. Document Revision History for the Stratix® 10 10 SX SoC Development Kit User Guide
1. Overview x
1.1. General Development Kit Description 1.2. Recommended Operating Conditions 1.3. Handling the Development Kit
2. Getting Started x
2.1. Installing Quartus® Prime Software 2.2. Installing the Intel® FPGA Download Cable 2.3. Installing the Intel SoC Embedded Development Suite (EDS) 2.4. Installing the Stratix® 10 SX SoC Development Kit Package
3. Development Kit Setup x
3.1. Inspect the Development Kit 3.2. Default Setup of the Development Kit 3.3. MAX® 10 System Controller Updates
4. Development Kit Components x
4.1. Development Kit Feature Summary 4.2. Board Components 4.3. Stratix® 10 SoC Device Overview 4.4. MAX® 10 System Controller Overview 4.5. FPGA Configuration 4.6. General User Input/Output 4.7. Connectors and Interfaces 4.8. Daughter Cards 4.9. System Memory 4.10. System Power
4.7. Connectors and Interfaces x
4.7.1. PCIe* Slot 4.7.2. ZQSFP+ 4.7.3. SFP+ 4.7.4. HDMI 4.7.5. SDI Port 4.7.6. MXP 4.7.7. Intel® FPGA Download Cable Direct Port (Debug Port) 4.7.8. FMC+ A/B Slot 4.7.9. FMC+ A/B LVDS Interfaces (LPC Pins) 4.7.10. LMK05028 Jitter Attenuator 4.7.11. FPGA-IOMAX10 Interface
4.8. Daughter Cards x
4.8.1. HPS IO-48 OOBE Daughter Card 4.8.2. HPS IO-48 NAND Flash Daughter Card 4.8.3. HPS Boot Flash Card
4.8.3. HPS Boot Flash Card x
4.8.3.1. Boot QSPI Flash Daughter Card 4.8.3.2. Boot MicroSD Daughter Card 4.8.3.3. Boot eMMC Daughter Card
4.9. System Memory x
4.9.1. FPGA Memory (DDR4 SO-DIMM) 4.9.2. HPS Memory (External 4 GB HILO x72 DDR4) 4.9.3. HPS I2C Interface
4.10. System Power x
4.10.1. Power Supply Options 4.10.2. Power Sequence 4.10.3. Power Distribution Network
5. Board Test System x
5.1. Preparing the Board 5.2. Running the BTS 5.3. Using the BTS
5.3. Using the BTS x
5.3.1. The Configure Menu 5.3.2. The GPIO Tab 5.3.3. The QSFP/SFP Tab 5.3.4. The PCIE Tab 5.3.5. The MXP Tab 5.3.6. The FMCA Tab 5.3.7. The FMCB Tab 5.3.8. The DDR4 Tab 5.3.9. Power Monitor 5.3.10. The Clock Control
A. Additional Information x
A.1. Modify the Stratix® 10 SX SoC Development Kit to use a battery for the BBRAM A.2. Modify the Stratix® 10 SX SoC Development Kit HPS DDR4 memory width and ECC configuration using the Golden Hardware Reference Design project A.3. Safety and Regulatory Information A.4. Compliance Information
A.3. Safety and Regulatory Information x
A.3.1. Safety Warnings A.3.2. Safety Cautions
A.4. Compliance Information x
A.4.1. Compliance and Conformity Statements
1. Overview
2. Getting Started
3. Development Kit Setup
4. Development Kit Components
5. Board Test System
A. Additional Information
B. Document Revision History for the Stratix® 10 10 SX SoC Development Kit User Guide

4.4. MAX® 10 System Controller Overview

MAX® 10 devices are single-chip, non-volatile low-cost programmable logic devices (PLDs) to integrate the optimal set of system components.

MAX® 10 devices are the ideal solution for system management, I/O expansion, communication control planes, industrial, automotive, and consumer applications.

The highlights of the MAX® 10 devices include:

  • Internally stored dual configuration flash
  • User flash memory
  • Instant on support
  • Integrated analog-to-digital converters (ADCs)
  • Single-chip Nios® II soft core processor support
Table 8.   Summary of Features for MAX® 10 Devices
Feature Description
Technology 55 nm TSMC Embedded Flash (Flash + SRAM) process technology
Packaging
  • Low cost, small form factor packages—support multiple packaging technologies and pin pitches
  • Multiple device densities with compatible package footprints for seamless migration between different device densities
  • RoHS6-compliant
Core architecture
  • 4-input look-up table (LUT) and single register logic element (LE)
  • LEs arranged in logic array block (LAB)
  • Embedded RAM and user flash memory
  • Clocks and PLLs
  • Embedded multiplier blocks
  • General purpose I/Os
Internal memory blocks
  • M9K—9 kilobits (Kb) memory blocks
  • Cascadable blocks to create RAM, dual port, and FIFO functions
User flash memory (UFM)
  • User accessible non-volatile storage
  • High speed operating frequency
  • Large memory size
  • High data retention
  • Multiple interface option
Embedded multiplier blocks
  • One 18 × 18 or two 9 × 9 multiplier modes
  • Cascadable blocks enabling creation of filters, arithmetic functions, and image processing pipelines
ADC
  • 12-bit successive approximation register (SAR) type
  • Up to 17 analog inputs
  • Cumulative speed up to 1 million samples per second ( MSPS)
  • Integrated temperature sensing capability
Clock networks
  • Global clocks support
  • High speed frequency in clock network
Internal oscillator Built-in internal ring oscillator
PLLs
  • Analog-based
  • Low jitter
  • High precision clock synthesis
  • Clock delay compensation
  • Zero delay buffering
  • Multiple output taps
General-purpose I/Os (GPIOs)
  • Multiple I/O standards support
  • On-chip termination (OCT)
  • Up to 830 megabits per second (Mbps) LVDS receiver, 800 Mbps LVDS transmitter
External memory interface (EMIF) 1 Supports up to 600 Mbps external memory interfaces:
  • DDR3, DDR3L, DDR2, LPDDR2 (on 10M16, 10M25, 10M40 and 10M50)
  • SRAM (Hardware support only)
Note: For 600 Mbps performance, –6 device speed grade is required. Performance varies according to device grade (commercial, industrial, or automotive) and device speed grade (–6 or –7). Refer to the MAX 10 Device Data Sheet or External Memory Interface Spec Estimator for more details.
Configuration
  • Internal configuration
  • JTAG
  • Advanced Encryption Standard (AES) 128-bit encryption and compression options
  • Flash memory data retention of 20 years at 85 °C
Flexible power supply schemes
  • Single- and dual-supply device options
  • Dynamically controlled input buffer power down
  • Sleep mode for dynamic power reduction
1 EMIF is only supported in selected MAX 10 device density and package combinations. Refer to the External Memory Interface User Guide for more information.
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