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A.1. Modify the Intel® Stratix® 10 SX SoC Development Kit to use a battery for the BBRAM
A.2. Modify the Intel® Stratix® 10 SX SoC Development Kit HPS DDR4 memory width and ECC configuration using the Golden Hardware Reference Design project
A.3. Safety and Regulatory Information
A.4. Compliance Information
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4.10.2. Power Sequence
The power-up/down sequence design follows power-up and power-down sequence requirements for Intel® Stratix® 10 devices, PCIe* Plug-in Card power up/down requirement, and FMC plug-in card power up/down requirement.
The following figures show the development kit power up/down sequence.
Figure 29. Power Up Sequence
Figure 30. Power Down Sequence
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