Intel® Stratix® 10 SX SoC Development Kit User Guide

ID 683303
Date 6/02/2023
Document Table of Contents

4.10.3. Power Distribution Network

The Intel® Stratix® 10 Development Kit uses the Intel® MAX® 10 CPLD (U46) as a power sequencer. J26 needs to be shorted to program Intel® MAX® 10 Power CPLD (U46). During normal operation, J26 needs to be open. The Intel® MAX® 10 CPLD monitors all power good signals, the 12V input voltage threshold signal (>10.2V), and turns on each FPGA power supply based on the power sequence requirements.

If 12V input voltage is below 12V input threshold voltage, the power down sequence is triggered. The Intel® MAX® 10 Power CPLD turns on the quick discharge circuit and turns off each power supply based on power down sequence requirements.

Figure 31. Power Distribution Network