Intel® Stratix® 10 SX SoC Development Kit User Guide

ID 683303
Date 6/02/2023
Document Table of Contents

5.3.8. The DDR4 Tab

This tab allows you to read and write DDR4 memory on the board.

Figure 42. The DDR4 Tab

The controls on this tab are described below.


Initiates DDR4 memory transaction performance analysis


Terminates transaction performance analysis

Performance Indicators

These controls display current transaction performance analysis information collected since you last clicked Start:
  • Write, Read and Total performance bars: Show the percentage of maximum theoretical data rate that requested transactions are able to achieve.
  • Write, Read and Total (MBps): Show the number of bytes analyzed per second.
  • Data Bus: 72 bits (8 bits ECC) wide and frequency is 1066 MHz double data rate. 2133 Mbps per pin.

Error Control

Displays data errors detected during analysis and allows you to insert errors
  • Detected errors: Displays the number of data errors detected in the hardware.
  • Inserted errors: Displays the number of errors inserted into the transmit data stream.
  • Insert Error: Inserts a one-word error into the transmit data stream each time you click the button. Insert Error is only enabled during transaction performance analysis.
  • Clear: Resets the Detected Errors counter and Inserted Errors counter to zero.

Address Range

Determines the number of addresses to use in each iteration of reads and writes