4.7.10. LMK05028 Jitter Attenuator
The LMK05028 device is a high-performance clock generator, jitter cleaner, and clock synchronizer with advanced reference clock selection and hitless switching to meet the stringent requirements of communications infrastructure applications.
The ultra-low jitter reduces bit error rates (BER) in high-speed serial links and improves signal to noise ratio (SNR) when clocking high-speed data converters.
The device has two independent PLL cores that can each synchronize or lock to one of four reference clock inputs, and the LMK05028 can generate up to eight output clocks with up to six different frequencies.
You can use the FPGA I2C port at FPGA pins BC25, BC26 to control LMK05028. LMK05028 3.3V I/O signals are connected to System MAX10 (U43) IO ports. You need to write code to connect these I/Os to FPGA 1.8V I/O ports. The J21 10-pin Header is used to connect the TI 05028 GUI port. You can use it to configure LMK05028.
Clock outputs from I/O ports (AW35, AW34, BA34, and AY34 pins) in 2B bank are connected to TI LMK05028.
|0||245 MHz or 297/1.001 MHz||AF9, AF10 in 4E Bank|
|1||122.88 MHz||Y38, Y37 in 1K Bank|
|2||122.88 MHz||AT41, AT40 in 1C Bank|
|3||122.88 MHz||D8, D9 (FALAP1, FALAN1) in FMCA|
|4||122.88 MHz||D8, D9 (FBLAP1, FBLAN1) in FMCB|
|5||122.88 MHz||AK12, AK 13 in 4E Bank|
|6||297 MHz||AK12, AK 13 in 4E Bank|
|7||644.53125 MHz||P9, P10 in bank 4M|
TI LMH1983 is used to generate SDI reference clocks. Four 3.3V IO signals (U43 pins: E17, F17, B21, B22) in the MAX10 system controller are connected to the LMH1983 FIN, VIN, HIN and INIT input pins. SDI users need to write code to map the four 3.3V IOs to the FGPA 1.8V IOs. The 27 MHz output clock is directly connected to clock cleaner input 2. The 148.5 MHz clock is connected to U15AN28 and An27 in IO bank 2F. The clock cleaner application can be found at this link.
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