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Ixiasoft
A.1. Modify the Intel® Stratix® 10 SX SoC Development Kit to use a battery for the BBRAM
A.2. Modify the Intel® Stratix® 10 SX SoC Development Kit HPS DDR4 memory width and ECC configuration using the Golden Hardware Reference Design project
A.3. Safety and Regulatory Information
A.4. Compliance Information
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Ixiasoft
4.1. Development Kit Feature Summary
Feature | Description |
---|---|
Programmable Logic |
|
HPS memory | 1066 MHz 4 GB 72-bit HILO memory card |
HPS Boot Flash (Flash Card) |
|
HPS IO48 OOBE Daughter Card |
|
HPS IO48 NAND Flash Daughter Card |
|
FPGA memory | 1200 MHz 16 GB DDR4 SO-DIMM MTA18ASF2G72HZ – 2G6 |
FPGA File Flash (Flash Card) |
|
Two V57.4 High Pin Count FMC+ Slots |
Note: FMC to PCIe cables are sold separately by Samtec. Please contact them directly regarding P/N HDR-201768-01-PCIEC
|
FPGA PCIe* Gen 1/2/3 x16 RC Slot |
|
FPGA Communication Ports |
|
FPGA Debug Ports | Intel® FPGA Download Cable Direct Port & JTAG |
FPGA Reference Clocks |
|
I2C Devices |
|
Intel® MAX® 10 Controller I/O CPLD Features |
|
Intel® MAX® 10 Power CPLD Sequencer | FPGA, PCIe, FMC+ slots power sequencer, Reset. |
Intel® MAX® 10 CPLD Features |
|
User I/O |
|
Power |
|
Mechanical |
|
System Monitor | Power, Voltage, Current |