OpenCL™ - BSP - Support Center

   

Environment Variable

Description

ACL_HAL_DEBUG

Set this variable to a value of 1 to 5 to increase debug output from the Hardware Abstraction Layer (HAL), which interfaces directly with the MMD layer.

ACL_PCIE_DEBUG

Set this variable to a value of 1 to 10000 to increase debug output from the MMD. This variable setting is useful for confirming that the version ID register was read correctly and the UniPHY IP cores are calibrated.

ACL_PCIE_JTAG_CABLE

Set this variable to override the default quartus_pgm argument that specifies the cable number. The default is cable 1. If there are multiple Intel® FPGA Download Cable, you can specify a particular cable by setting this variable.

ACL_PCIE_JTAG_DEVICE_INDEX

Set this variable to override the default quartus_pgm argument that specifies the FPGA device index. By default, this variable has a value of 1. If the FPGA is not the first device in the JTAG chain, you can customize the value.

ACL_PCIE_USE_JTAG_PROGRAMMING

Set this variable to force the MMD to reprogram the FPGA using the JTAG cable instead of Partial Reconfiguration.

ACL_PCIE_DMA_USE_MSI

Set this variable if you want to use MSI for direct memory access (DMA) transfers on Windows*.

Title

Description

Getting Started with OpenCL™ part 1

This video describes the out-of-box procedure for running two applications, OpenCL™ HelloWorld and OpenCL™ fast Fourier transform (FFT) on the Cyclone® V SoC using a Windows* machine.

Getting Started with OpenCL™ part 2

This video describes the out-of-box procedure for running two applications, OpenCL™ HelloWorld and OpenCL™ FFT on the Cyclone® V SoC using a Windows* machine.

Getting Started with OpenCL part 3

This video describes the out-of-box procedure for running two applications, OpenCL™ HelloWorld and OpenCL™ FFT on the Cyclone® V SoC using a Windows* machine.

Getting Started with OpenCL Part 4

This video describes the out-of-box procedure for running two applications, OpenCL™ HelloWorld and OpenCL™ FFT on the Cyclone® V SoC using a Windows* machine.

Getting Started with OpenCL part 5

This video describes the out-of-box procedure for running two applications, OpenCL™ HelloWorld and OpenCL™ FFT on the Cyclone® V SoC using a Windows* machine.

How to Package Custom Verilog Modules/Designs as OpenCL™ Libraries

The video discusses why customers could potentially use this feature to have their custom processing blocks (RTL) in OpenCL™ kernel code. The video explains the design example such as the make files, config files, and explains the compilation flow. The video also show a demo of the design example.

OpenCL™ on Intel FPGA SoC FPGA (Linux Host) – Part 1 – Tools Download and Setup

This video shows you how to download, install, and configure the tools required to develop OpenCL™ kernels and host code targeting Intel FPGA SoC FPGAs.

OpenCL™ on Intel FPGA SoC FPGA (Linux Host) – Part 2 – Running the Vector Add Example with the Emulator

This video shows you how to download and compile an example OpenCL™ application targeting the emulator that is built into the Intel FPGA OpenCL™.

OpenCL™ on Intel FPGA SoC FPGA (Linux Host) – Part 3 – Kernel and Host Code Compilation for SoC FPGA

This video shows you how to compile the OpenCL™ kernel and host code targeting the FPGA and processor of the Cyclone® V SoC FPGA.

OpenCL™ on Intel FPGA SoC FPGA (Linux Host) – Part 4 – Setup of the Runtime Environment

This video shows you how to set up the Cyclone® V SoC board to run the OpenCL™ example, and execute the host code and kernel on the board.