AN 812: Platform Designer System Design Tutorial

ID 683855
Date 4/02/2018
Document Table of Contents
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Platform Designer System Design Tutorial

The Platform Designer system integration tool for Intel FPGA and SoC devices automatically generates interconnect logic to connect intellectual property (IP) components and subsystems. Using Platform Designer saves time and effort in the design process. Platform Designer inherits the ease of use of Platform Designer (Standard). In addition, Platform Designer introduces hierarchical isolation between system interconnect and IP components. This tutorial is for users who have basic knowledge of Intel® Quartus® Prime Pro Edition software and Platform Designer (Standard), and want to experience the new features of Platform Designer.

This tutorial guides you through the following processes:

  • Building systems in Platform Designer, and integrating those systems into an Intel® Quartus® Prime Pro Edition project.
  • Explains the different user flows between Platform Designer (Standard) and Platform Designer.
  • Demonstrates some of the new features of Platform Designer and how it increases efficiency and flexibility for team-based design.

The procedures in this tutorial provide you with a template to design a system that uses various test patterns to test an external memory device. The final system contains the following components:

  • A processor subsystem which contains an Intel® Nios® II/e core. The subsystem also includes an on-chip RAM to store the software code and a JTAG UART to communicate and display the memory test results in the host PC's console.
  • A memory tester subsystem to interact with an SDRAM controller.
  • The memory tester subsystem consists of a pattern generator subsystem, a pattern checker subsystem, a memory tester, a pattern writer, and a pattern reader.
  • The pattern generator subsystem consists of a custom pattern generator, a pseudo random binary sequence (PRBS) pattern generator, along with a multiplexer (MUX) to select between these two.
  • A data pattern checker subsystem consisting of a custom pattern checker, a pseudo random binary sequence (PRBS) pattern checker, along with a demultiplexer (DEMUX).
  • Pattern writer and pattern reader subsystems that interacts with the SDRAM controller.
  • A SDRAM controller to control the off-chip DDR SDRAM device under test.
Figure 1.  Platform Designer System

There are four broad steps in this tutorial:

  1. Build a processor subsystem from scratch in Platform Designer.
  2. Build a top-level Platform Designer system with memory tester subsystem instantiated as a generic component.
  3. Implement a generic component.
  4. Create a Nios® II software application and run the design on a FPGA.