AN 812: Platform Designer System Design Tutorial

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ID 683855
Date 4/02/2018
Public
Document Table of Contents
Document Table of Contents x
Platform Designer System Design Tutorial
Platform Designer System Design Tutorial x
Hardware and Software Requirements Download and Install the Tutorial Design Files Build the Hardware Design Build Software Applications and Download the Design AN 812: Platform Designer System Design Tutorial Revision History
Build the Hardware Design x
Open the Intel® Quartus® Prime Pro Edition Project Build a Platform Designer System with a Top-Down Approach Implement the Memory Tester Subsystem
Build a Platform Designer System with a Top-Down Approach x
Add a Processor Subsystem to the Top-Level Build the Processor Subsystem Add External Memory Interface Instantiate a Memory Tester Subsystem as a Generic Component Connect and Generate IP Files Examples of Platform Designer Generic Components
Build the Processor Subsystem x
Add a Nios® II Processor Add RAM, JTAG UART, and Avalon-MM Pipeline Bridge Connect cpu_subsystem Components Platform Designer and Platform Designer (Standard) Differences
Implement the Memory Tester Subsystem x
Add Clock, Reset, and Avalon-MM components Add Pre-Built Systems and Memory Test Microcore Components Export Signals, Set Base Address Assignments, and Connect Memory Tester Interface Components Resolve Interface Requirements and Value Mismatches Replace the memory_tester_subsystem Generic Component Synchronize IP Results
Build Software Applications and Download the Design x
Hardware setup Run the Bash Script
Platform Designer System Design Tutorial

Add a Nios® II Processor

  1. Type nios in the search box of the IP Catalog and double-click Nios® II Processor.
  2. In the Select an Implementation parameter editor, select the Nios® II /e processor.
  3. To add the Nios® II/e processor to the design, click Finish.
  4. Right-click the name of the Nios® II processor component and click Rename. Type cpu to change the name.
  5. In the Export column, double-click the entry corresponding to the Reset Output for the cpu component and rename it cpu_jtag_debug_reset.

    Errors regarding reset and exception slaves can be resolved after you add connections.

    Figure 9. cpu_subsystem Export Naming
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