Add Clock, Reset, and Avalon-MM components
Add Pre-Built Systems and Memory Test Microcore Components
Export Signals, Set Base Address Assignments, and Connect Memory Tester Interface Components
Resolve Interface Requirements and Value Mismatches
Replace the memory_tester_subsystem Generic Component
Synchronize IP Results
Platform Designer and Platform Designer (Standard) Differences
Platform Designer introduces a hierarchical isolation between system interconnect and IP components by saving the parameters of each IP component in a .ip file under <project folder>/ip/<Platform Designer system name> and saving of the system interconnect in a .qsys file under <project folder>. The RTL of each .ip or .qsys file can be generated in isolation as it contains the full information required to reproduce the state of the RTL. There are no unresolved dependencies between files.
For example, Platform Designer saves the Nios® II processor parameterization in <project folder>/ip/cpu_subsystem/cpu_subsystem_ nios2_gen2_0.ip, and the system interconnect in <project folder>/cpu_subsystem.qsys.
Figure 16. File Location for Nios® II Processor IP File
Platform Designer and Platform Designer (Standard) differ also differ in how they handle IP files:
- Platform Designer requires that you include the .qsys file along with a list of .ip files associated with that Platform Designer project. The Intel® Quartus® Prime Pro Edition software manages this for you after you save your Platform Designer project.
- The older Platform Designer (Standard) tool saves both component instantiation and system interconnects in a .qsys file. When integrating a Platform Designer (Standard) system to a Intel® Quartus® Prime project, you only need to include a single Intel® Quartus® Prime IP file (.qip).