AN 812: Platform Designer System Design Tutorial

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ID 683855
Date 4/02/2018
Public
Document Table of Contents
Document Table of Contents x
Platform Designer System Design Tutorial
Platform Designer System Design Tutorial x
Hardware and Software Requirements Download and Install the Tutorial Design Files Build the Hardware Design Build Software Applications and Download the Design AN 812: Platform Designer System Design Tutorial Revision History
Build the Hardware Design x
Open the Intel® Quartus® Prime Pro Edition Project Build a Platform Designer System with a Top-Down Approach Implement the Memory Tester Subsystem
Build a Platform Designer System with a Top-Down Approach x
Add a Processor Subsystem to the Top-Level Build the Processor Subsystem Add External Memory Interface Instantiate a Memory Tester Subsystem as a Generic Component Connect and Generate IP Files Examples of Platform Designer Generic Components
Build the Processor Subsystem x
Add a Nios® II Processor Add RAM, JTAG UART, and Avalon-MM Pipeline Bridge Connect cpu_subsystem Components Platform Designer and Platform Designer (Standard) Differences
Implement the Memory Tester Subsystem x
Add Clock, Reset, and Avalon-MM components Add Pre-Built Systems and Memory Test Microcore Components Export Signals, Set Base Address Assignments, and Connect Memory Tester Interface Components Resolve Interface Requirements and Value Mismatches Replace the memory_tester_subsystem Generic Component Synchronize IP Results
Build Software Applications and Download the Design x
Hardware setup Run the Bash Script
Platform Designer System Design Tutorial

Replace the memory_tester_subsystem Generic Component

Next, replace the generic component with the memory_tester_subsystem implementation:
  1. Click Tools > Platform Designer to launch Platform Designer. Browse to the top_system.qsys file and click Open.
  2. Right-click the memory_tester_subsystem component and click Remove.
  3. In the IP Catalog, browse to the System folder and double-click to memory_tester_subsystem. Keep the same name and update the connections.
  4. Right-click the name of the top_system_subsystem_0 and click Rename. Type memory_tester_subsystem.
  5. Verify and complete connections based on the following table:
    Source Component/Signal Target Component/Signal
    ext_clk/out_clk
    • ext_reset/clk
    • cpu_subsystem/cpu_clk
    • emif_0/pll_ref_clk
    ext_reset/out_reset
    • cpu_subsystem/cpu_reset
    • cpu_subsystem/mem_reset
    • memory_tester_subsystem/reset
    • emif_0/global_reset_n
    cpu_subsystem/cpu_jtag_debug_reset
    • cpu_subsystem/cpu_reset
    • cpu_subsystem/mem_reset
    • memory_tester_subsystem/reset
    • emif_0/global_reset_n
    cpu_subsystem/master
    • memory_tester_subsystem/slave
    memory_tester_subsystem/read_master
    • emif_0/ctrl_amm_0
    memory_tester_subsystem/write_master
    • emif_0/ctrl_amm_0
    emif_0/emif_usr_clk
    • cpu_subsystem/mem_clk
    • memory_tester_subsystem/clk
    emif_0/emif_usr_reset_n
    • cpu_subsystem/mem_reset
  6. Compare the connections to the following figure:
    Figure 41. memory_tester_subsystem Implementation Connections
  7. Click File > Save.
  8. Click Generate > Generate HDL.
  9. Click Generate.
  10. Close the current Platform Designer project when generation is done.
The files in included with this design are Verilog (.v) files, but you can also use VHDL (.vhdl) in your design if you prefer.
Level Two Title