AN 812: Platform Designer System Design Tutorial

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ID 683855
Date 4/02/2018
Public
Document Table of Contents
Document Table of Contents x
Platform Designer System Design Tutorial
Platform Designer System Design Tutorial x
Hardware and Software Requirements Download and Install the Tutorial Design Files Build the Hardware Design Build Software Applications and Download the Design AN 812: Platform Designer System Design Tutorial Revision History
Build the Hardware Design x
Open the Intel® Quartus® Prime Pro Edition Project Build a Platform Designer System with a Top-Down Approach Implement the Memory Tester Subsystem
Build a Platform Designer System with a Top-Down Approach x
Add a Processor Subsystem to the Top-Level Build the Processor Subsystem Add External Memory Interface Instantiate a Memory Tester Subsystem as a Generic Component Connect and Generate IP Files Examples of Platform Designer Generic Components
Build the Processor Subsystem x
Add a Nios® II Processor Add RAM, JTAG UART, and Avalon-MM Pipeline Bridge Connect cpu_subsystem Components Platform Designer and Platform Designer (Standard) Differences
Implement the Memory Tester Subsystem x
Add Clock, Reset, and Avalon-MM components Add Pre-Built Systems and Memory Test Microcore Components Export Signals, Set Base Address Assignments, and Connect Memory Tester Interface Components Resolve Interface Requirements and Value Mismatches Replace the memory_tester_subsystem Generic Component Synchronize IP Results
Build Software Applications and Download the Design x
Hardware setup Run the Bash Script
Platform Designer System Design Tutorial

Download and Install the Tutorial Design Files

  1. On the Platform Designer Tutorial Design Example page, under Using this Design Example, click Platform Designer Tutorial Design Example (.zip) to download and install the tutorial design files for the Platform Designer tutorial.
  2. Extract the contents of the archive file to a directory on your computer. Do not use spaces in the directory path name.

The qsys_pro_tutorial_design_Arria_10_17p0.zip contains the following project files and is referred to as <project folder> in the rest of the document.

Table 1.  Qsys Pro Design Tutorial Project Files
Folder Structure Description
/complete_design The final design. You can use this design as a reference and guidance while you follow the tutorial. You may also use the prebuilt systems in it if you want to skip certain steps of this tutorial.
/ip The folder that stores IP component source files. The pattern_checker_system and pattern_generator_system are pre-generated for you.
/memory_tester_ip The folder that contains source files for all custom components.
/software This folder contains source code for building Nios® II software applications and two scripts that automate this process for you.
A10.qpf An Intel® Quartus® Prime Project file (.qpf).
A10.qsf An Intel® Quartus® Prime Settings file (.qsf), containing pre-defined pin assignments.
memory_tester_search_path.ipx IP Index file (.ipx) that specifies the path to the source files of the custom components.
memory_tester_subsystem_bb.ipxact The .ipxact file that defines the interfaces for your generic component.
my_constraints.sdc A Synopsys Design Constraints, or SDC, file (.sdc) containing timing constraints.
pattern_checker_system.qsys Pre-built Platform Designer System file (.qsys).
pattern_generator_system.qsys Pre-built Platform Designer System file (.qsys).
top_level.v Top-level Verilog Design file (.v) .
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