Article ID: 000080153 Content Type: Product Information & Documentation Last Reviewed: 04/18/2023

How to close timing on competing hold and setup violations in Intel® Arria® 10 FPGAs?


  • Quartus® II Subscription Edition

    In Intel® Arria® 10 devices, the Quartus® II software fitter automatically packs registers into an Adaptive Logic Module (ALM) to optimize area. If a hold-critical register gets packed in the same ALM as its driving LUT, the router will add wire in front of the LUT to avoid hold time violations. This can negatively affect a critical path setup going through the same LUT, making it difficult to fix both setup and hold time violations around this structure.


    A new Quartus Settings File (.QSF) assignment is available that prevents the automatic packing of the register and its driving LUT into the same ALM. This allows the router to add the necessary hold-fixing wire directly in front of the register and does not negatively affect the critical path setup through the LUT itself.

    To prevent register/LUT packing, use the following assignment:

    set_instance_assignment -name QII_AUTO_PACKED_REGISTERS OFF -to <inst_name>

    This assignment is available in the Quartus II software version 14.0 Intel Arria 10 FPGA Edition and later. Future releases of the Quartus II software are scheduled to handle this automatically.

    Related Products

    This article applies to 3 products

    Intel® Arria® 10 GT FPGA
    Intel® Arria® 10 GX FPGA
    Intel® Arria® 10 SX SoC FPGA