Intel® FPGA SDK for OpenCL™ - Support Center

Runtime Debug Variables
There are certain environment variables that can be set to get more debug information while running the host application. These are Intel® FPGA SDK for OpenCL™ specific environment variables, which can help diagnose problems with custom platform designs. The following table lists all of these environment variables as well as describes them in detail.
Environment Variable Title Description

ACL_HAL_DEBUG

Set this variable to a value of 1 to 5 to increase debug output from the hardware abstraction layer (HAL), which interfaces directly with the MMD layer.

ACL_PCIE_DEBUG

Set this variable to a value of 1 to 10,000 to increase debug output from the MMD. This variable setting is useful for confirming that the version ID register was read correctly and the UniPHY IP cores are calibrated.

ACL_PCIE_JTAG_CABLE

Set this variable to override the default quartus_pgm argument that specifies the cable number. The default is cable 1. If there are multiple Intel® FPGA Download Cables, you can specify a particular cable by setting this variable.

ACL_PCIE_JTAG_DEVICE_INDEX

Set this variable to override the default quartus_pgm argument that specifies the FPGA device index. By default, this variable has a value of 1. If the FPGA is not the first device in the JTAG chain, you can customize the value.

ACL_PCIE_USE_JTAG_PROGRAMMING

Set this variable to force the MMD to reprogram the FPGA using the JTAG cable instead of partial reconfiguration.

ACL_PCIE_DMA_USE_MSI

Set this variable if you want to use MSI for direct memory access (DMA) transfers on Windows* OS.

FPGA Knowledge Base Articles

Error: Assert failure at /XXX/llvm/lib/Transforms/FPGATransforms/TransformPrintf.cpp(715)

Error: Unknown device part 1SG280LU2F50E2VG

Segmentation fault in acl_event_is_valid () using clEnqueueFIllBufer()

** Error: ./../../ip/kernel_system/kernel_system_sys_description_rom/acl_rom_module_10/sim/acl_rom_module.v(77): Module 'acl_reset_handler' is not defined.

Available MLAB in OpenCL report is 0

Can I use existing Synopsys Design Compiler (DC) ASIC synthesis scripts for FPGA synthesis in the DC FPGA software?

Can Intel® Stratix® 10 GX FPGA Development Kit support PCIe gen3x16 for OpenCL?

compiler error : Unrecognized function call: acl.external.iowr

Compiler Error: Argument in 'constant' address space cannot be stored in heterogeneous global memory.

Compiling an OpenCL kernel Using Both the --profile and -g0 Intel FPGA SDK for OpenCL Offline Compiler Command Options Does Not Remove Source Code from the .aocx File

Does the printf routine in the Nios™ embedded processor software development kit (SDK) support floating-point data types?

Emulation of an OpenCL Design Might Consume All CPU Resources and Cause a Fatal Error

Error (13224): Verilog HDL or VHDL error at <kernel_filename>.v: ansi port p_avm_printf_addrhello_world_enable cannot be redeclared

Error (16045): Instance "ccip_std_afu|bsp_logic_inst|board_inst" instantiates undefined entity "board" File

Error (16045): Instance "ccip_std_afu|bsp_logic_inst|board_inst" instantiates undefined entity "board" File: /home/anchen/Downloads/dla/build/dla/build/bsp_logic.sv Line: 133

Error (16045): Instance "ccip_std_afu|bsp_logic_inst|board_inst" instantiates undefined entity "board" File: /home/anchen/Downloads/dla/build/dla/build/bsp_logic.sv Line: 133

Error (18212): Cannot load final snapshot for partition "root_partition”

Error (18590): The imported netlist contains settings that are not supported by the current version of the software.

Error (213009): File name "output_files/afu_import.green_region.pmsf" does not exist or can't be read

Error (297008): Can't create database directory for project in project directory

Error (XXXXX): Cannot generate Atom Netlist File because family Stratix 10 is not installed

Error (XXXXX): Cannot generate Atom Netlist File because family Stratix 10 is not installed

Error message : "Error: Optimizer FAILED -dbg-info-enabled --grif --soft-elementary-math=false --fas=false --wiicm-disable=true "kernel_top.1.bc" -o "kernel_top.kwgid.bc"

Error: Unable to find Intel(R) FPGA OpenCL platform

Error: "X Error of failed request: BadValue"

Error: alt_pr.avmm_slave (0x0..0x3f) is outside the master's address range (0x0..0x7)

Error: aoc: The Intel(R) Kernel Builder for OpenCL(TM) compiler (ioc64) can not be found

error: aocl_opt: Too many positional arguments specified. Can specify at most 1 positional arguments

Error: Assert failure at /XXX/llvm/lib/Analysis/FPGAAnalysis/MemoryAccessAnalysis.cpp(1537)

Error: Assert failure at ACLMemUtils.cpp(510)

Error: board.pipe_stage_host_ctrl.m0: alt_pr.avmm_slave cannot be at 0xcfb0 (0xcf80 or 0xcfc0 are acceptable)

Error: board.pipe_stage_host_ctrl.m0: version_id.s (0xcfc0..0xcfc3) overlaps alt_pr.avmm_slave (0xcfb0..0xcfef)

Error: cannot find board_env.xml in BSP location

ERROR: CL_INVALID_KERNEL_NAME

Error: Could not find fit report afu_opencl_kernel.fit.rpt under compile directory

Error: device enumeration failed

error: function 'read_channel_altera' is not supported by the Intel(R) FPGA SDK for OpenCL(TM), and no user definition is provided

error: function 'write_channel_altera' is not supported by the Intel(R) FPGA SDK for OpenCL(TM), and no user definition is provided

Error: ip-generate FAILED

Error: kernel_mem_mm_bridge_0: deviceFamily "Arria 10" is out of range: "Cyclone 10 GX", "None", "Unknown"

Error: kernel_mem_mm_bridge_0: deviceFamily "Arria 10" is out of range: "Cyclone 10 GX", "None", "Unknown"

Error: OpenCL Notification Callback: Global work size in one dimension exceeds device limits Failed to launch kernel

ERROR: packager tool failed to run

error: redefinition of 'filter_coeffs' constant int filter_coeffs[2 * 2 * 2 * FILTER_TAPS] = {

Error: System integrator FAILED

ERROR: Unable to find Altera OpenCL Platform

ERROR: Unable to find Intel(R) FPGA OpenCL platform during emulation

error: Unexpected use of HDL library function(s) (possibly due to taking the address of the function)!

error: unknown argument: '--fmax=300'

Error: Unknown device part 10AX115S2F45I1SG

Error: Unknown device part 10AX115S2F45I1SG

Error: Unknown device part 1SG280LU2F50E2VG

ERROR: UNRECOGNIZED ERROR CODE (-1001), Location: ../common/src/AOCLUtils/opencl.cpp:297, Query for number of platforms failed

Error: WDC_PCiScanDevices failed.

export ACL_QSH_COMPILE_CMD="quartus_sh --flow recompile top -c flat" is not working in 17.0

External I/O Channels Unavailable in Custom Platforms Ported from the Altera Stratix V Network Reference Platform

For MAX 10 designs, the Quartus II software issues "Error (125095): Part name...invalid" and "Error (281000): Part name...illegal" errors

Host-to-Device Memory Transfers Exceeding 8 KB Might Cause a Fatal Error in the Windows Version of the Altera Arria 10 GX FPGA Development Kit Reference Platform

How can the non-volatile flash be programmed if the Intel® SDK for OpenCL™ command “aocl program” causes the computer to reboot?

How do I compile an OpenCL kernel using the latest version of the Intel® SDK for OpenCL™ with a Board Support Package (BSP) from a previous version?

How should I use the OpenCL function clReleaseEvent to avoid memory leaks?

How to determine how many FPGA boards the system includes?

How to handle OpenCL library AVALON_MEM element ?

Installing an unsigned driver might cause an error in the Altera SDK for OpenCL running on Windows 8.1

Intel FPGA for OpenCL kernel naming restrictions

Intel FPGA SDK for OpenCL Version 17.0 Does Not Support Ubuntu Operating Systems

Internal Compiler Error: Missing start cycle information for queried node: sync_out

Internal Error: Sub-system: QHD, File: /quartus/comp/qhd/qhd_database_model_utils.cpp

Internal Error: Sub-system: QSYM, File: /quartus/ccl/qsym/qsym_namespace.cpp, Line: 264 String table for 43 is 5844 (ID: 721426136, Symbol: 5848)

Internal Error: Sub-system: QSYM, File: /quartus/ccl/qsym/qsym_namespace.cpp, Line: 264 String table for 43 is 5844 (ID: 721426136, Symbol: 5848)

Internal Error: Sub-system: VPR20KMAIN, File: /quartus/fitter/vpr20k/altera_arch_common/altera_arch_re_network_tools.cpp, Line: 883

jtagconfig:No JTAG hardware available

Kernel execution and memory data transfer can not run simultaneously even there's no event dependency in host code

Linker Error: undefined reference to nios_output_memory_access', at config/nios/nios.c:2540

Nios II GCC compiler options: -march, -mbmx, -mno-bmx, -mcdx, -mno-cdx

No expected output when running "aocl env" on emulation aocx file

Open CL kernel autorun for emulator mode

OpenCL Error: Hard routing constraints for signal could not be satisfied

OpenCL Error: ip-generate FAILED

The Technology Map Viewer (Post-Mapping) does not load the schematic of the design netlist when Analysis & Synthesis is complete

Unable to restart autorun kernel on emulator on 17.0

Unable to unlock /intelFPGA_pro/17.1.1/hld/installed_packages

Using the Altera SDK for OpenCL Version 16.0.1 to Compile an OpenCL Design that Targets a 16.0 Version of the Arria 10 Reference or Custom Platform Results in a Fatal Error

Warning: Please use -board=<value> instead of --board <value>

Warning: Please use -profile instead of --profile

Warning: Please use -report instead of --report

WARNING: Selected File does not have the same path as the file's path stored in .aocx file! May result in blank data

warning: xx.cl:x:x: loop not unrolled: the optimizer was unable to perform the requested transformation; the transformation might be disabled or specified as part of an unsupported transformation ordering

What does the “container” mean in the report.html container for Intel® FPGA OpenCL™ SDK?

When running nios-debug or any other utility that uses the MDI/OCI connection via the parallel-port direct (aka parport2k) method, why do I see a Driver Load Failed message box which prevents further action involving JTAG debugging?

Where are the OpenCL™ board support packages (BSP) for the development kits?

Where do I install the FCD (FPGA Client Driver) *.fcd file using OpenCL SDK tools version 17.0?

Which function should I use when linking the FCD (FPGA Client driver) to the host application?

Why are the Altera OpenCL SDK definitions num_vector_lanes and num_copies not in the 13.0sp1 documentation?

Why do I get bad performance when compiling vector add example design with Intel® FPGA SDK for OpenCL™?

Why do I get Error (114016): Out of memory in module quartus_syn when compiling architectures in the Intel® FPGA Deep Learning Acceleration Suite?

Why do I get the different available resource when compiling the same OpenCL™ design with different versions of Intel® FPGA OpenCL™ SDK?

Why do I get the error “CL_INVALID_ARG_SIZE” when using type long long as an OpenCL™ kernel argument in the host code?

Why do I get the error “No JTAG hardware available” when running jtagconfig in Linux CentOS or Ubuntu?

Why do I get the error “Unable to determine the execution environment” when running the “aocl version” command in the Intel SDK for OpenCL?

OpenCL™ Quick Videos

Video Title

Video Description

How to Run Hello World and (Other Programs) with OpenCL™ on Cyclone® V SoC Using Windows* Part 1

This video describes the out-of-box procedure for running two applications, OpenCL™ HelloWorld and OpenCL fast Fourier transform (FFT) on the Cyclone® V SoC using a Windows* machine.

How to Run Hello World and (Other Programs) with OpenCL on Cyclone V SoC Using Windows Part 2

This video describes the out-of-box procedure for running two applications, OpenCL HelloWorld and OpenCL FFT on the Cyclone V SoC using a Windows machine.

How to Run Hello World and (Other Programs) with OpenCL on Cyclone V SoC Using Windows Part 3

This video describes the out-of-box procedure for running two applications, OpenCL HelloWorld and OpenCL FFT on the Cyclone V SoC using a Windows machine.

How to Run Hello World and (Other Programs) with OpenCL on Cyclone V SoC Using Windows Part 4

This video describes the out-of-box procedure for running two applications, OpenCL HelloWorld and OpenCL FFT on the Cyclone V SoC using a Windows machine.

How to Run Hello World and (Other Programs) with OpenCL on Cyclone V SoC Using Windows Part 5

This video describes the out-of-box procedure for running two applications, OpenCL HelloWorld and OpenCL FFT on the Cyclone V SoC using a Windows machine.

How to Package Custom Verilog Modules/Designs as OpenCL Libraries

The video discusses why customers could potentially use this feature to have their custom processing blocks (RTL) in OpenCL kernel code. The video explains the design example, such as the makefiles and config files, and explains the compilation flow. The video also shows a demo of the design example.

OpenCL on Altera® SoC FPGA (Linux* Host) – Part 1 – Tools Download and Setup

This video shows you how to download, install, and configure the tools required to develop OpenCL kernels and host code targeting Altera® SoC FPGAs.

OpenCL on Altera SoC FPGA (Linux Host) – Part 2 – Running the Vector Add Example with the Emulator

This video shows you how to download and compile an example OpenCL application targeting the emulator that is built into the OpenCL.

OpenCL on Altera SoC FPGA (Linux Host) – Part 3 – Kernel and Host Code Compilation for SoC FPGA

This video shows you how to compile the OpenCL kernel and host code targeting the FPGA and processor of the Cyclone V SoC FPGA.

OpenCL on Altera SoC FPGA (Linux Host) – Part 4 – Setup of the Runtime Environment

This video shows you how to set up the Cyclone V SoC board to run the OpenCL example and execute the host code and kernel on the board.