Article ID: 000086285 Content Type: Error Messages Last Reviewed: 03/15/2019

Error: board.pipe_stage_host_ctrl.m0: version_id.s (0xcfc0..0xcfc3) overlaps alt_pr.avmm_slave (0xcfb0..0xcfef)

Environment

  • Intel® Arria® 10 FPGAs and SoC FPGAs
  • Intel® Quartus® Prime Pro Edition
  • Intel® FPGA SDK for OpenCL™
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    You may see this error message when the Intel® Arria® 10 GX BSP board.sys file is opened in Qsys and you choose the option “Sync All System Infos” using Quartus® Prime software version 17.0

    Resolution

    To work around this issue change the address to 0xcf00 of the PR IP.  If you recompile the base revision then this address change must also be reflected in the following file linux64/driver/hw_pcie_constants.h by changing the ACL_PRCONTROLLER_OFFSET value to 0xcf00.

    This problem has been fixed starting in Quartus Prime software version 17.1.

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