This example contains an optimized time-domain finite impulse response (FIR) filter kernel based on the HPEC Challenge Benchmark suite. FIR filters can be implemented efficiently on an FPGA by using shift registers to maximize data reuse. This example demonstrates how to efficiently describe a FIR filter in Open Computing Language (OpenCLTM), which is part of the class of applications that use sliding windows. The specific computation implemented in this example is a 128-tap complex single-precision floating-point time-domain FIR filter.
FIR Filter Performance
- Efficient 1D sliding window buffer
- Single work-item kernel
- Detailed optimization guide (see the Downloads section)
- Third-party benchmark
The design example provides source code for the OpenCL device (.cl) as well as the host application. For compiling the host application, the Linux* package includes a Makefile and the Windows package includes a Microsoft Visual Studio 2010 project.
The following downloads are provided for this example:
- v17.1 x64 Linux package (.tar.gz)
- v17.1 x64 Windows package (.zip)
- Time-Domain FIR Filter Optimization Guide (PDF)
The use of this design is governed by, and subject to, the terms and conditions of the hardware reference design license agreement.
Software and Hardware Requirements
This design example requires the following tools:
- Intel® FPGA software v17.1 or later
- Intel FPGA SDK for OpenCL™ v17.1 or later
- On Linux: GNU Make and gcc
- On Windows: Microsoft Visual Studio 2010
To download the Intel design tools, visit the OpenCL download page. The requirements for the underlying operating system are the same as those of the Intel FPGA SDK for OpenCL.
OpenCL and the OpenCL logo are trademarks of Apple Inc. used by permission by Khronos.
* Product is based on a published Khronos Specification, and has passed the Khronos Conformance Testing Process. Current conformance status can be found at www.khronos.org/conformance.