Optical Flow Design Example

Recommended for:

  • Device: Cyclone® V

  • Quartus®: v17.1



This benchmark demonstrates a OpenCLTM implementation of the Lucas Kanade Optical Flow algorithm. The implementation is based on the following paper: Pyramidal Implementation of the Lucas Kanade Feature Tracker Description of the algorithm, by Jean-Yves Bouguet.

This design example implements a dense, non-iterative, non-pyramidal version with 52x52 window size. It was designed for platforms with smaller FPGA devices, specifically the Cyclone® V SoC Development Kit.

Optical Flow Performance


  • Single work-item kernel
  • Sliding window design pattern
  • Resource usage reduction techniques


The design example provides source code for the OpenCL device (.cl) as well as the host application. For compiling the host application, the Linux* package includes a Makefile and the Windows* package includes a Microsoft Visual Studio 2010* project.

The following downloads are provided for this example:

The use of this design is governed by, and subject to, the terms and conditions of the hardware reference design license agreement.

Software and Hardware Requirements

This design example requires the following tools:

  • Intel® FPGA software v17.1 or later
  • Intel® FPGA SDK for OpenCL™ v17.1 or later
  • On Linux: GNU Make and gcc
  • On Windows*: Microsoft Visual Studio 2010*
  • To compile to arm32 architecture, also get SoCEDS v17.1 or later.
    • For Windows, you will need gmake.
    • VisualStudio project cannot compile to arm32.

To download the Intel design tools, visit the OpenCL download page. The requirements for the underlying operating system are the same as those of the Intel FPGA SDK for OpenCL.

OpenCL and the OpenCL logo are trademarks of Apple Inc. used by permission by Khronos.

* Product is based on a published Khronos Specification, and has passed the Khronos Conformance Testing Process. Current conformance status can be found at www.khronos.org/conformance.