FPGA Knowledge Base
The Intel® FPGA Knowledge Base page provides links to applicable articles that span a variety of FPGA related issues. Use the FILTER BY left navigation to refine your selection by device family and Intel® Quartus Prime Software edition and version. Additional page user instructions are located at the bottom of this page.
10212 Results
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Why does the Quartus® Prime Pro Edition Software version 24.1 observe 17 clock cycles when using the Generic Serial Flash Interface IP(GSFI IP)? This problem is caused by 2 modules in the GSFI IP: the if_ctrl (interface control) module, which is used to interface to the QSPI flash, and the cmd (command) module, which is used to generate the flash command. The additional flash clock only impacts read operations on the flash, which are read data or read register operations. It does not impact write operations. |
05/28/2025 |
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Internal Error: Sub-system: S2T, File: /quartus/tsm/s2t/s2t_visitors.cpp, Line: 2063 Due to a problem in the Quartus® Prime Pro Edition Software version 24.3 or earlier, you may see this internal error during the Analysis & Synthesis stage. |
05/28/2025 |
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Warning(332158): Clock uncertainty characteristics of the Agilex™ 7 FPGA device family are preliminary Due to a problem in the Quartus® Prime Pro Edition Software version 25.1 and earlier, you may encounter this warning message during the Fitter stage when compiling designs targeting Agilex™ 7 FPGA devices. Although the release notes indicate the timing model is final, the warning message may still appear. |
05/28/2025 |
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Why is the Siemens EDA* AXI3 Bus Functional Model (BFM) license feature (mgcvipaeaxi) not generated in the license file? The AXI3 BFM is no longer supported in Siemens EDA* AXI Verification IP Suite License (FPGA Edition) and is no longer included in license files generated in the FPGA Self Service Licensing Center (SSLC). |
05/28/2025 |
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Which Quartus® Prime versions support the Generic Flash Programmer? Generic Flash Programmer is supported starting from Quartus® Prime Standard Edition software version 18.1.1 and later, and Quartus® Prime Pro Edition software version 19.1 and later. |
05/26/2025 |
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Why do I see Unconstrained Output Ports at the EMIF unused pins when compiling the Agilex™ 7 FPGA M-Series EMIF IP? Due to a problem in the Quartus® Prime Pro Edition Software version 25.1 or earlier, you may see Unconstrained Output Ports at EMIF unused pins when compiling the Agilex™ 7 FPGA M-Series EMIF IP. |
05/26/2025 |
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Why do several IP design examples fail on the Agilex™ 7 FPGA Series Transceiver SoC Development Kit? The following Intel® FPGA IP Cores generate example designs for the Intel Agilex® 7 FPGA-Series Transceiver SoC Development Kit with incorrect VID settings. |
05/26/2025 |
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Are there any functional or security updates for the Quartus® Prime Standard Edition Software version 23.1.1? The Quartus® Prime Standard Edition Software version 23.1.1 Patch 1.01std includes functional and security updates. Users should keep their software up-to-date and follow the technical recommendations to help improve security. |
05/23/2025 |
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Error: s0: Error during execution of Due to a problem in the Quartus® Prime Standard Edition software version 18.1 and earlier, Platform Designer system generation may fail and exit with this error message. This only happens in Windows* 10 OS. |
05/23/2025 |
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Is there a known issue with simulating the Cyclone® 10 FPGA LP PLL IP using Verilog? Due to a problem in the Quartus® Prime Standard Edition software version 17.0, the PLL simulation model is not instantiated for Cyclone® 10 FPGA LP devices when performing Verilog simulation. This issue does not apply when simulating the Cyclone® 10 FPGA LP PLL IP using VHDL. |
05/23/2025 |
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** Error: (qrun-13321) name Due to a problem in the Quartus® Prime Pro Edition Software version 24.1, you might see the qrun-13321 error during the simulator compilation stage when simulating a design using Questa* FPGA Edition or Siemens EDA QuestaSim* simulator with the Qrun flow option enabled. This error happens if any of the included paths in the automatically-generated modelsim_com.f file contains a space. |
05/23/2025 |
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Critical Warning (24035): The exported partition, Due to a problem in the Quartus® Prime Pro Edition Software version 24.2 and earlier, you might see this critical warning when exporting the QDB partition with a higher-level wrapper. This critical warning can be safely ignored during QDB partition exporting. This critical warning can be safely ignored during QDB partition exporting. |
05/23/2025 |
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Error (22595): Quartus Prime software does not support entity Due to a problem in the Quartus® Prime Pro Edition Software version 24.2 and earlier, you might see this error when compiling the project using the command quartus_sh --flow compile <project_name> in the Nios® V Command Shell. You might also see this error if compiling the project with the Quartus® GUI launched from the Nios® V Command Shell. |
05/23/2025 |
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Internal Error: Sub-system: STA, File: /quartus/tsm/sta/sta_clock_mgr.cpp, Line: 8971 Due to a problem in the Quartus® Prime Standard Edition software version 19.1, you may see this error during the synthesis stage of compilation. This internal error occurs when using Synplify Pro* FPGA Synthesis software for synthesis. |
05/23/2025 |
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What timing constraints do I need to apply to the automatically generated altera_reserved_* JTAG pins in my design? Many in-system debugging tools, such as the Signal Tap Logic Analyzer, the In-System Sources and Probes, or the Nios® II debugger, use the JTAG interface in Altera® FPGAs. The Quartus® Prime Software automatically generates the altera_reserved_tck, altera_reserved_tms, altera_reserved_tdi, and altera_reserved_tdo pins for a design that uses a JTAG accessible module. Because of this, the Timing Analyzer flags these signals as unconstrained when an unconstrained path report is generated. When you debug your design |
05/23/2025 |
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Embedded Peripherals IP User Guide - Altera® FPGA MII to RMII Converter Core - Table 461. The Parameter Scenario is incorrect Table 461. Parameter Usage Scenario, in section 50. Intel® FPGA MII to RMII Converter Core in the Embedded Peripherals IP User Guide is incorrect |
05/23/2025 |
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Why do I see timing violations in my design with JTAG-Over-Protocol FPGA IP? Due to a problem in the Quartus® Prime Pro Edition Software version 24.3 and earlier, you might see timing violations in SignalTap-related nodes when your design includes the JTAG-Over-Protocol FPGA IP. |
05/23/2025 |
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Why do link partners report errors when connected to the F-Tile PMA/FEC Direct PHY FPGA IP variant with the Datapath clocking mode parameter is set to PMA, the PMA width parameter set to 16 and the Enable TX double width transfer parameter is unselected? Due to a problem in the Quartus® Prime Pro Edition Software version 23.3 and later, link partner devices might report bit errors when connected to the F-Tile PMA/FEC Direct PHY FPGA IP variants where the Datapath clocking mode parameter is set to PMA, the PMA width parameter set to 16 and the Enable TX double width transfer parameter is unselected? |
05/23/2025 |
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Why does my F-Tile Ethernet FPGA Hard IP variant with the “Link fault generation” parameter set to “Bidirectional” start transmitting invalid packets when the transmit MAC stops sending “remote fault” ordered sets during link fault recovery? Due to a problem in the Quartus® Prime Pro Edition Software version 24.1, the F-Tile Ethernet FPGA Hard IP variant with the “Link fault generation” parameter set to “Bidirectional” will transmit invalid packets when the TX MAC stops sending “remote fault” ordered sets during link fault recovery. These packets can have various issues, such as “invalid FCS” or length errors, and will cease to be transmitted after the transmit pipeline of the Ethernet MAC has been emptied. Following the transmission of these invalid packets, the Ethernet MAC will start to transmit valid Ethernet packets. |
05/23/2025 |
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Why does my F-Tile Ethernet Multirate IP variant with the “Enable auto-negotiation and link training” parameter enabled and the “Link fault generation” parameter set to “Bidirectional” fail to complete “auto-negotiation and link training”? Due to a problem in the Quartus® Prime Pro Edition Software version 24.3, the F-Tile Ethernet Multirate IP variant with the “Enable auto-negotiation and link training” parameter enabled and the “Link fault generation” parameter set to “Bidirectional” will fail to complete auto-negotiation and link training. |
05/23/2025 |
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