Article ID: 000080483 Content Type: Error Messages Last Reviewed: 05/23/2025

Internal Error: Sub-system: STA, File: /quartus/tsm/sta/sta_clock_mgr.cpp, Line: 8971

Environment

    Intel® Quartus® Prime Standard Edition
BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

Due to a problem in the Quartus® Prime Standard Edition software version 19.1, you may see this error during the synthesis stage of compilation. This internal error occurs when using Synplify Pro* FPGA Synthesis software for synthesis.

Resolution

To workaround this problem, use this assignment:

set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER ON

Related Products

This article applies to 11 products

Arria® V FPGAs and SoC FPGAs
Intel® Cyclone® 10 LP FPGA
MAX® V CPLDs
Cyclone® V FPGAs and SoC FPGAs
Stratix® IV FPGAs
Intel® Arria® 10 FPGAs and SoC FPGAs
MAX® II CPLDs
Arria® II FPGAs
Cyclone® IV FPGAs
Intel® MAX® 10 FPGAs
Stratix® V FPGAs

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