Critical Issue
The following IP Cores generate example designs for the Agilex™ 7 FPGA Series Transceiver SoC Development Kit with incorrect VID settings.
1) Serial Lite IV IP
2) Interlaken (2nd Generation) IP
3) Triple-Speed Ethernet IP
4) E-Tile Dynamic Reconfiguration IP
5) E-Tile Hard IP for Ethernet and CPRI PHY IP
6) JESD204B IP
7) JESD204C IP
8) Ethernet Subsystem IP
The correct VID settings can be found in section 6.1, Add SmartVID settings in the Quartus® Prime QSF file of the Agilex™ F-Series Transceiver-SoC Development Kit User Guide.
Update the design examples with the correct VID settings as shown below:
set_global_assignment -name PWRMGT_BUS_SPEED_MODE "100 KHZ"
set_global_assignment -name PWRMGT_SLAVE_DEVICE0_ADDRESS 42
set_global_assignment -name PWRMGT_SLAVE_DEVICE1_ADDRESS 00
set_global_assignment -name PWRMGT_SLAVE_DEVICE2_ADDRESS 00
set_global_assignment -name PWRMGT_SLAVE_DEVICE3_ADDRESS 00
set_global_assignment -name PWRMGT_SLAVE_DEVICE4_ADDRESS 00
set_global_assignment -name PWRMGT_SLAVE_DEVICE5_ADDRESS 00
set_global_assignment -name PWRMGT_SLAVE_DEVICE6_ADDRESS 00
set_global_assignment -name PWRMGT_SLAVE_DEVICE7_ADDRESS 00
set_global_assignment -name USE_PWRMGT_SCL SDM_IO0
set_global_assignment -name USE_PWRMGT_SDA SDM_IO12
set_global_assignment -name USE_CONF_DONE SDM_IO16
set_global_assignment -name VID_OPERATION_MODE "PMBUS MASTER"
set_global_assignment -name PWRMGT_VOLTAGE_OUTPUT_FORMAT "LINEAR FORMAT"
set_global_assignment -name PWRMGT_LINEAR_FORMAT_N "-13"
set_global_assignment -name PWRMGT_TRANSLATED_VOLTAGE_VALUE_UNIT VOLTS
This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition Software.