Is there a known issue with simulating the Cyclone® 10 FPGA LP PLL IP using Verilog?

Due to a problem in the Quartus® Prime Standard Edition software version 17.0, the PLL simulation model is not instantiated for Cyclone® 10 FPGA LP devices when performing Verilog simulation. This issue does not apply when simulating the Cyclone® 10 FPGA LP PLL IP using VHDL.

To fix this issue, install the patch below on top of Quartus® Prime Standard version 17.0 and follow the instructions to add extra steps in your simulation run script.

if ![file isdirectory verilog_libs] {
    file mkdir verilog_libs
}

vlib verilog_libs/altera_mf_ver
vmap altera_mf_ver ./verilog_libs/altera_mf_ver
vlog -vlog01compat -work altera_mf_ver {c:/intelfpga/17.0/quartus/eda/sim_lib/altera_mf.v}

quartus-17.0std-0.12std-windows.exe

quartus-17.0std-0.12std-linux.run

quartus-17.0std-0.12std-readme.txt

This problem is fixed beginning with the Quartus® Prime Standard Edition software version 18.0.