Article ID: 000074685 Content Type: Troubleshooting Last Reviewed: 05/23/2025

Is there a known issue with simulating the Cyclone® 10 FPGA LP PLL IP using Verilog?

Environment

  • Intel® Quartus® Prime Standard Edition
  • PLL Intel® FPGA IP
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the Quartus® Prime Standard Edition software version 17.0, the PLL simulation model is not instantiated for Cyclone® 10 FPGA LP devices when performing Verilog simulation. This issue does not apply when simulating the Cyclone® 10 FPGA LP PLL IP using VHDL.

    Resolution

    To fix this issue, install the patch below on top of Quartus® Prime Standard version 17.0 and follow the instructions to add extra steps in your simulation run script.

    if ![file isdirectory verilog_libs] {
        file mkdir verilog_libs
    }

    vlib verilog_libs/altera_mf_ver
    vmap altera_mf_ver ./verilog_libs/altera_mf_ver
    vlog -vlog01compat -work altera_mf_ver {c:/intelfpga/17.0/quartus/eda/sim_lib/altera_mf.v}

     

    quartus-17.0std-0.12std-windows.exe

    quartus-17.0std-0.12std-linux.run

    quartus-17.0std-0.12std-readme.txt

     


    This problem is fixed beginning with the Quartus® Prime Standard Edition software version 18.0.

     

    Related Products

    This article applies to 1 products

    Intel® Cyclone® 10 LP FPGA