Article ID: 000098404 Content Type: Troubleshooting Last Reviewed: 05/23/2025

Why do link partners report errors when connected to the F-Tile PMA/FEC Direct PHY FPGA IP variant with the Datapath clocking mode parameter is set to PMA, the PMA width parameter set to 16 and the Enable TX double width transfer parameter is unselected?

Environment

    Intel® Quartus® Prime Pro Edition
BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

Due to a problem in the Quartus® Prime Pro Edition Software version 23.3 and later, link partner devices might report bit errors when connected to the F-Tile PMA/FEC Direct PHY FPGA IP variants where the Datapath clocking mode parameter is set to PMA, the PMA width parameter set to 16 and the Enable TX double width transfer parameter is unselected?

 

Resolution

There is no workaround for this problem.

This problem has been fixed starting in version 24.3 of the Quartus® Prime Pro Edition Software.
 

Related Products

This article applies to 1 products

Intel Agilex® 7 FPGAs and SoC FPGAs

1

Need more help?

Contact support

Disclaimer

1

All postings and use of the content on this site are subject to Intel.com Terms of Use.