Why does my F-Tile Ethernet FPGA Hard IP variant with the “Link fault generation” parameter set to “Bidirectional” start transmitting invalid packets when the transmit MAC stops sending “remote fault” ordered sets during link fault recovery?

Due to a problem in the Quartus® Prime Pro Edition Software version 24.1, the F-Tile Ethernet FPGA Hard IP variant with the “Link fault generation” parameter set to “Bidirectional” will transmit invalid packets when the TX MAC stops sending “remote fault” ordered sets during link fault recovery. These packets can have various issues, such as “invalid FCS” or length errors, and will cease to be transmitted after the transmit pipeline of the Ethernet MAC has been emptied. Following the transmission of these invalid packets, the Ethernet MAC will start to transmit valid Ethernet packets.

No work around to this problem exists. 

This problem has been fixed starting in version 24.3 of the Quartus® Prime Pro Edition Software.