Why do I get bad performance when compiling vector add example design with Intel® FPGA SDK for OpenCL™?

To work around this problem, add an attribute  to vector_add.cl which sets the required work group size.

  __attribute__((reqd_work_group_size(1, 1, 1)))
  __kernel void vector_add(__global const float *x, 
                           __global const float *y, 
                           __global float *restrict z)
  {
      // get index of the work item
      int index = get_global_id(0);
      // add the vector elements
      z[index] = x[index] + y[index];
  }

The problem is scheduled to be fixed in a future release of the the Intel® FPGA SDK for OpenCL™.