Video Downscaling Design Example

Recommended for:

  • Device: Stratix® V

  • Quartus®: v17.1



This example demonstrates an Open Computing Language (OpenCL™) implementation of a fixed ratio (2/3) video downscaler. The example takes 1080p YUV 4:2:0 video, downscales it to 720p and displays the result on the screen.

This example implements a two-pass downscaler, where each pass downscales the input along the horizontal direction and outputs the result in a transposed order. Each pass invokes two kernels that communicate using Intel's channels vendor extension. The partitioning into two kernels allows each kernel to efficiently access global memory.

Video Downscaling Performance


  • Sliding window design pattern
  • Single work-item kernels
  • Kernel-to-kernel channels
  • Memory access pattern optimizations


The design example provides source code for the OpenCL device (.cl) as well as the host application. For compiling the host application, the Linux* package includes a Makefile and the Windows* package includes a Microsoft* Visual Studio 2010 project.

The following downloads are provided for this example:

The use of this design is governed by, and subject to, the terms and conditions of the hardware reference design license agreement.

Software and Hardware Requirements

This design example requires the following tools:

  • Intel® FPGA software v17.1 or later
  • Intel FPGA SDK for OpenCL v17.1 or later
  • On Linux: GNU Make and gcc
  • On Windows: Microsoft Visual Studio 2010

To download the Intel design tools, visit the OpenCL download page. The requirements for the underlying operating system are the same as those of the Intel FPGA SDK for OpenCL.

OpenCL and the OpenCL logo are trademarks of Apple Inc. used by permission by Khronos.

* Product is based on a published Khronos Specification, and has passed the Khronos Conformance Testing Process. Current conformance status can be found at