Transceiver PHY IP Support Center

Table 1 - Device Variant and Feature Support

Device

Intel Cyclone 10

Intel Arria 10

Intel Stratix 10

Intel Agilex

Device Variant

GX

SX(3)

GX(3)

GT(4)

GX/SX L-Tile

GX/SX H-Tile

MX/TX E-Tile

AGF E-Tile

Maximum Data Rate
(Chip-to-Chip)(1)(7)


GX Channels

12.5 Gbps

17.4 Gbps

17.4 Gbps

17.4 Gbps

17.4 Gbps

N/A

N/A

GXT Channels

N/A

N/A

25.8 Gbps

26.6 Gbps

28.3 Gbps

28.3 Gbps

N/A

GXE Channels

N/A

N/A
N/A
N/A

N/A

28.9 Gbps (NRZ)

57.8 Gbps (PAM4)

28.9 Gbps (NRZ)

57.8 Gbps (PAM4)

Maximum Data Rate
(Backplane)(8)

GX Channels

6.6Gbps

12.5 Gbps

12.5 Gbps

12.5 Gbps

28.3 Gbps 28.3 Gbps N/A

GXT Channels

N/A

N/A


GXE Channels

N/A

N/A

N/A

N/A

N/A

28.9 Gbps (NRZ)

57.8 Gbps (PAM4)

28.9 Gbps (NRZ)

57.8 Gbps (PAM4)

Maximum Channels per device

GX Channels

12

96

72

96

96 N/A

N/A

GXT Channels

N/A

N/A

6

32

64

24

N/A

GXE Channels

N/A

N/A

N/A

N/A

N/A 120

24 (and 32 P-Tile)

Hard IP One PCIe Gen2 x4 per device. PCIe* Gen3 x8 up to 4 per device PCIe Gen3 x16 up to 4 per device PCIe Gen3 x16 up to 4 per device 50/100 Gbps Ethernet MACup to 4 per device PCIe Gen3 x16 up to 4 per device SR-IOV (four PF/2K VF) (6) 10G/25G/100G Ethernet with optional 1588 capability + RS-FEC (528, 514)/RS-FEC (544, 514) 10G/25G/100G Ethernet with optional 1588 capability + RS-FEC (528, 514)/RS-FEC (544, 514)
SR-IOV support is not available.

Title

Type

Description

Building Interfaces with Intel Arria 10 High-Speed Transceivers

Instructor-Led

Learn the architecture of Intel Arria 10 and Intel Cyclone 10 FPGA transceivers and then the flow for incorporating them into an FPGA design.

Transceiver Basics for 20 nm and 28 nm Devices

Online

Learn the basic building blocks that are found in 20 and 28 nm FPGA transceivers used to support a range of high-speed protocols.

Intel Stratix 10 Transceiver Basics

Online

Learn the basic building blocks that are found in Intel Stratix 10 FPGA transceivers used to support a range of high-speed protocols.

Transceiver Toolkit for Intel Arria 10 Devices

Online

Learn how to debug and dynamically fine tune the analog settings of your Intel Arria 10 and Intel Cyclone 10 FPGA transceivers.

Advanced Signal Conditioning for Intel Arria 10 FPGA Transceivers

Online

Learn the analog capabilities of Intel Arria 10 FPGA transceivers and how to use them to improve link performance.

Building a Generation 10 Transceiver PHY Layer

Online

Learn how to build a custom transceiver implementation using the Intel Arria 10 and Intel Cyclone 10 FPGA transceiver IP blocks.

Building an Intel Stratix 10 FPGA Transceiver PHY Layer

Online

Learn how to define the three resources that make up an Intel Stratix 10 FPGA transceiver PHY layer solution, namely, the transceiver PHY, the transceiver PLL and the transceiver reset controller.

Generation 10 Transceiver Clocking

Online

Learn the clocking resources that are found in Intel Arria 10 and Intel Cyclone 10 FPGA transceiver blocks.

Title

Description

How to Dynamically Reconfigure PMA Analog Parameters for Intel Cyclone 10 GX

Learn the implementation of Intel Cyclone 10 GX FPGA Native PHY PMA analog parameters using direct reconfiguration flow.

How to Perform the Intel Cyclone 10 GX Dynamic Reconfiguration with fPLL Switching and Channel Reconfiguration Using Direct Write Method

Learn how to perform the transceiver dynamic reconfiguration functional simulation with Intel Cyclone 10 GX FPGA fractional phase-locked loop (PLL) switching and channel reconfiguration using the direct write method.

How to Perform Intel Cyclone 10 GX Native PHY ATX PLL Switching and Channel Reconfiguration

Learn how to perform the functional simulation with Intel Cyclone 10 GX FPGA Native PHY ATX PLL switching, channel reconfiguration with embedded streamer, and channel recalibration.

How to Switch the CDR refclk Selection Using Embedded Streamer and Reconfiguration Profiles in Intel Arria 10 Native PHY

Learn how to perform dynamic reconfiguration to switch the clock data recovery (CDR) refclks with embedded streamer and multiple reconfiguration profiles in the Intel Arria 10 device.

How to Configure Two FPGAs that is Externally Connected through SMA Cables Using Transceiver Toolkit

Learn how to configure two device under test (DUTs), launch transceiver (XCVR) toolkits, perform chip-to-chip interface, and find the right analog settings.

How to Perform Dynamic Reconfiguration to Switch TX PLLs for the Intel Arria 10 Transceiver Using Embedded Streamer

Learn how to perform dynamic reconfiguration to switch transmitter (TX) PLLs for the Intel Arria 10 FPGA transceiver using embedded streamer.

Title

Description

Intel Arria 10 Device Configuration of a Simplex Transceiver

Watch this video to learn how to place an Intel Arria 10 device simplex transceiver with dynamic reconfiguration in the same physical transceiver channel.

Dynamic Reconfiguration of an Intel Arria 10 Device Transceiver

Watch this video to learn how to perform data rate changes using transmit (TX) phase-locked loop (PLL) switching and the embedded streamer in Intel Arria 10 devices.

How to Use the Transceiver Toolkit Part 1

Watch this four-part video to learn how to use the Transceiver Toolkit application, demonstrated on an Intel Arria 10 FPGA Development Kit. This video explains how to get the optimal physical medium attachment (PMA) settings for the transceiver.

How to Use the Transceiver Toolkit Part 2

Watch this four-part video to learn how to use the Transceiver Toolkit application, demonstrated on an Intel Arria 10 FPGA Development Kit. This video explains how to get the optimal PMA settings for the transceiver.

How to Use the Transceiver Toolkit Part 3

Watch this four-part video to learn how to use the Transceiver Toolkit application, demonstrated on an Intel Arria 10 FPGA Development Kit. This video explains how to get the optimal PMA settings for the transceiver.

How to Use the Transceiver Toolkit Part 4

Watch this four-part video to learn how to use the Transceiver Toolkit application, demonstrated on an Intel Arria 10 FPGA Development Kit. This video explains how to get the optimal PMA settings for the transceiver.

Intel Arria 10 Transceivers: Pre-Emphasis Basics

Learn the basics of the Intel Arria 10 Transceiver Pre-Emphasis feature. Compare simulated waveform versus silicon measurements.

Performing Dynamic Reconfiguration for the Intel Arria 10 Device Transceiver

Watch this video to learn how to perform data rate changes using TX PLL switching with the embedded streamer in Intel Arria 10 devices.

Reconfigure Intel Arria 10 Device Transceivers Using Embedded Streamer

Watch this video to learn how to perform dynamic reconfiguration with the Intel Arria 10 device transceiver Standard PCS using the embedded streamer.

Use the IBIS-AMI Model to Estimate Signal Integrity of Intel Arria 10 Device Transceiver

Watch this video to learn how to perform a signal integrity simulation with the Intel Arria 10 device transceiver IBIS-AMI model in the Intel® Advanced Link Analyzer. Additionally, this video covers eye diagram reporting.