Transceiver PHY IP Support Center
The Transceiver PHY IP Support Center provides information on how to select, design, and implement Transceiver PHY IP links.
The Transceiver PHY IP support center provides information on how to select, design, and implement transceiver links for Agilex™ 7, Agilex™ 5, Agilex™ 3, Stratix® 10, Arria® 10, and Cyclone® 10 devices. There are also guidelines on how to bring up your system and debug the transceiver links. This page is organized into categories that align with a high-speed transceiver system design flow from start to finish.
Get additional support for Agilex™ 7 FPGA Interface Protocol Design, Agilex™ 5 FPGA Interface Protocol Design, and Agilex™ 3 FPGA Interface Protocol Design step-by-step guided journeys for standard development flows surfacing the key critical resources and documentation.
For other devices, search the Device and Product Support Collections.
Getting Started
- Agilex™ 7 FPGAs and SoCs Device Data Sheet: F-Series and I-Series
- Agilex™ 7 FPGAs and SoCs Device Overview
- Agilex™ 7 Device Design Guidelines
- E-Tile Transceiver PHY User Guide
- F-Tile Ethernet FPGA Hard IP User Guide
- Agilex™ 5 FPGAs and SoCs Device Overview
- Agilex™ 5 FPGAs and SoCs Device Data Sheet
- Agilex™ 3 FPGAs and SoCs Device Overview
- Agilex™ 3 FPGAs and SoCs Device Data Sheet
1. Device and IP Selection
Which FPGA Device Family Should I Use?
Table 1 - Device Variant Maximum Transceiver Data Rate and Channel Count Feature Support | |||||||||||||
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Device | Agilex™ 7 | Agilex™ 5 | Agilex™ 3 | Stratix® 10 | Arria® 10 | Cyclone® 10 | |||||||
Device Variant | F-Series E-Tile |
D-Series | E-Series (Group A) |
E-Series (Group B) |
C-Series | GX/SX L-Tile |
GX/SX H-Tile |
MX/TX E-Tile |
SX3, 5 | GX3, 5 | GT4 | GX | |
Maximum Data Rate (Chip-to-Chip)1, 6 | GX Channels | - | - | - | - | - | - | 17.4 Gbps | - | 17.4 Gbps | 17.4 Gbps | 17.4 Gbps | 12.5 Gbps |
GXT Channels | - | - | - | - | - | 26.6 Gbps | 28.3 Gbps | 28.3 Gbps | - | - | 25.8 Gbps | - | |
GXE Channels | 28.9 Gbps (NRZ) 57.8 Gbps (PAM4) |
- | - | - | - | - | - | 28.9 Gbps (NRZ) 57.8 Gbps (PAM4) |
- | - | - | - | |
GTS Channels | - | 28.1 Gbps | 28.1 Gbps | 17.16 Gbps | 12.5 Gbps | - | - | - | - | - | - | - | |
Maximum Data Rate (Backplane)7 | GX Channels | - | - | - | - | - | 12.5 Gbps | 28.3 Gbps | 28.3 Gbps | 12.5 Gbps | 12.5 Gbps | 12.5 Gbps | 6.6Gbps |
GXT Channels | - | - | - | - | - | 12.5 Gbps | 28.3 Gbps | 28.3 Gbps | - | 12.5 Gbps | 12.5 Gbps | - | |
GXE Channels | 28.9 Gbps (NRZ) 57.8 Gbps (PAM4) |
- | - | - | - | - | - | 28.9 Gbps (NRZ) 57.8 Gbps (PAM4) |
- | - | - | - | |
GTS Channels | - | 28.1 Gbps | 28.1 Gbps | 17.16 Gbps | 12.5 Gbps | - | - | - | - | - | - | - | |
Maximum Channels per device | GX Channels | - | - | - | - | - | 96 | 96 | - | 96 | 72 | 72 | 12 |
GXT Channels | - | - | - | - | - | 32 | 64 | 24 | - | 6 | 6 | - | |
GXE Channels | 24 (and 32 P-Tile) | - | - | - | - | - | - | 120 | - | - | - | - | |
GTS Channels | - | 32 | 24 | 24 | 4 | - | - | - | - | - | - | - | |
Notes:
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Table 2 - Interface Hard IP Device Variant and Feature Support | ||||||||||||
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Device | Agilex™ 7 | Agilex™ 5 | Agilex™ 3 | Stratix® 10 | Arria® 10 | Cyclone® 10 | ||||||
Device Variant | F-Series E-Tile |
D-Series | E-Series (Group A) |
E-Series (Group B) |
C-Series | GX/SX L-Tile |
GX/SX H-Tile |
MX/TX E-Tile |
SX | GX | GT | GX |
PCIe Hard IP | One PCIe Gen2 x4 per device. | Up to four PCIe 4.0 x8 | Up to six PCIe 4.0 x4 | Up to six PCIe 3.0 x4 or PCIe 4.0 x42 | One PCIe 3.0 x4 | PCIe Gen3 x16 up to 4 per device | - | - | PCIe Gen3 x16 up to 4 per device | PCIe Gen3 x16 up to 4 per device | PCIe Gen3 x16 up to 4 per device | PCIe* Gen3 x8 up to 4 per device |
Ethernet Hard IP | 10G/25G/100G Ethernet with optional 1588 capability + RS-FEC (528, 514)/RS-FEC (544, 514) | 10G/25G Ethernet with optional 1588 PTP capability + Firecode FEC/RS-FEC (528, 514) | 10G/25G Ethernet with optional 1588 PTP capability + Firecode FEC/RS-FEC (528, 514) | 10G Ethernet with optional 1588 PTP capability + Firecode FEC | 10G Ethernet with optional 1588 PTP capability + Firecode FEC | - | 50/100 Gbps Ethernet MACup to 4 per device PCIe Gen3 x16 up to 4 per device SR-IOV (four PF/2K VF)1 | 10G/25G/100G Ethernet with optional 1588 capability + RS-FEC (528, 514)/RS-FEC (544, 514) | - | - | - | - |
USB 3.1 Hard IP3 | - | One channel with USB 3.1 controller in HPS block | One channel with USB 3.1 controller in HPS block | One channel with USB 3.1 controller in HPS block | One channel with USB 3.1 controller in HPS block | - | - | - | - | - | - | - |
Notes:
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FPGA Device Datasheets
- Agilex™ 7 FPGAs and SoCs Device Data Sheet: F-Series and I-Series
- Agilex™ 7 FPGAs and SoCs Device Data Sheet: M-Series
- Agilex™ 5 FPGAs and SoCs Device Data Sheet
- Agilex™ 3 FPGAs and SoCs Device Data Sheet
- Stratix® 10 Device Datasheet
- Arria® 10 Device Datasheet
- Cyclone® 10 GX Device Datasheet
Additional Resources
Refer to the Overview chapter of the following user guides:
Topic | Agilex™ 7 | Agilex™ 5 | Agilex™ 3 | Stratix® 10 | Arria® 10 | Cyclone® 10 |
---|---|---|---|---|---|---|
Additional Resources | GTS Transceiver PHY User Guide: Agilex™ 5 FPGAs and SoCs | GTS Transceiver PHY User Guide: Agilex™ 3 FPGAs and SoCs |
2. Design Flow and IP Integration
Where Can I Find Information on Transceiver Usage?
Use the E-Tile Channel Placement Tool in conjunction with the Stratix® 10 Device Family Pin Connection Guidelines, to swiftly plan protocol placements in the E-Tile prior to reading comprehensive documentation and implementing designs in the Quartus® Prime software. The Excel-based E-Tile Channel Placement Tool is supplemented with instruction, legend, revision, and protocols tabs.
Topic | Agilex™ 7 | Agilex™ 5 | Agilex™ 3 | Stratix® 10 | Arria® 10 | Cyclone® 10 |
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What Design Recommendations Should I Consider? | ||||||
Where Can I Find Information on Transceiver PHY IP Integration? | ||||||
Where Can I Find Information on Transceiver PHY IP Register Mapping? | ||||||
Analog Settings Guidelines |
3. Board Design and Power Management
Topic | Agilex™ 7 | Agilex™ 5 | Agilex™ 3 | Stratix® 10 | Arria® 10 | Cyclone® 10 | Max® 10 | Stratix® V | Arria® V | Cyclone® V | Max® V |
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Board Design Guidelines |
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Pin Connection Guidelines | |||||||||||
Schematic Review | |||||||||||
Power Management |
Simulation Models & Tools
The Advanced Link Analyzer is a state-of-the art jitter/noise eye link analysis tool that allows you to quickly and easily evaluate high-speed serial link performance. It is an ideal pre-design tool to help you understand how FPGA solutions can fit your system requirements. It is also an effective tool for post-design support to assist in debug and validation.
Models
Development Kit User Guides
Topic | Agilex™ 7 | Stratix® 10 | Arria® 10 |
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Development Kit User Guides |
4. Interoperability and Standards Testing
Topic | Agilex™ 7 | Agilex™ 5 | Agilex™ 3 | Stratix® 10 | Arria® 10 | Cyclone® 10 | Max® 10 |
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Applications | |||||||
Models |
5. Design Examples and Reference Designs
Topic | Agilex™ 7 | Agilex™ 5 | Stratix® 10 | Arria® 10 | Cyclone® 10 |
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Design Examples and Reference Designs | Altera Example Designs on GitHub |
6. Training Courses and Videos
Recommended Training Courses
Topic |
Description |
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E-Tile Clocking | Learn about the reference clocks available on the E-tile, and E-tile transceiver datapath clocks are generated and distributed. |
GTS Transceiver Basics Training | This training introduces the basics of the Agilex™ 5 and Agilex 3 FPGA GTS transceiver is optimized for a wide range of applications in markets such as broadcasting, industrial, medical and communications, to name a few. This course will introduce you to the GTS transceivers and the building blocks that make up them. |
Transceiver Toolkit Training | This online training will introduce you to the Transceiver Toolkit found in the Quartus® Prime Pro software and features like Auto Sweep and the Eye Viewer. |
Learn the basic building blocks that are found in 20 and 28 nm FPGA transceivers used to support a range of high-speed protocols. |
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Learn the basic building blocks that are found in Stratix® 10 FPGA transceivers used to support a range of high-speed protocols. |
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Building an Stratix® 10 FPGA Transceiver PHY Layer | Learn how to define the three resources that make up an Stratix® 10 FPGA transceiver PHY layer solution, namely, the transceiver PHY, the transceiver PLL and the transceiver reset controller. |
Learn how to debug and dynamically fine tune the analog settings of your Arria® 10 and Cyclone® 10 FPGA transceivers. |
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Advanced Signal Conditioning for Arria® 10 FPGA Transceivers |
Learn the analog capabilities of Arria® 10 FPGA transceivers and how to use them to improve link performance. |
Learn how to build a custom transceiver implementation using the Arria® 10 and Cyclone® 10 FPGA transceiver IP blocks. |
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Learn the clocking resources that are found in Arria® 10 and Cyclone® 10 FPGA transceiver blocks. |
Topic |
Description |
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F-Tile Channel Placement Tool | The F-Tile Channel Placement Tool, in conjunction with the Device Family Pin Connection Guidelines, allows you to swiftly plan protocol placements in the product prior to reading comprehensive documentation and implementing designs in Quartus® Prime Pro software. |
FPGA Quick Videos
Title |
Description |
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17G Transceiver Demo Video | Watch the first Agilex™ 5 FPGA E-Series Group B devices running 17Gbps transceivers in our lab. |
Watch this video to learn how to place an Arria® 10 device simplex transceiver with dynamic reconfiguration in the same physical transceiver channel. |
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Watch this video to learn how to perform data rate changes using transmit (TX) phase-locked loop (PLL) switching and the embedded streamer in Arria® 10 devices. |
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Watch this four-part video to learn how to use the Transceiver Toolkit application, demonstrated on an Arria® 10 FPGA Development Kit. This video explains how to get the optimal physical medium attachment (PMA) settings for the transceiver. |
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Watch this four-part video to learn how to use the Transceiver Toolkit application, demonstrated on an Arria® 10 FPGA Development Kit. This video explains how to get the optimal PMA settings for the transceiver. |
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Watch this four-part video to learn how to use the Transceiver Toolkit application, demonstrated on an Arria® 10 FPGA Development Kit. This video explains how to get the optimal PMA settings for the transceiver. |
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Watch this four-part video to learn how to use the Transceiver Toolkit application, demonstrated on an Arria® 10 FPGA Development Kit. This video explains how to get the optimal PMA settings for the transceiver. |
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Learn the basics of the Arria® 10 Transceiver Pre-Emphasis feature. Compare simulated waveform versus silicon measurements. |
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Performing Dynamic Reconfiguration for the Arria® 10 Device Transceiver |
Watch this video to learn how to perform data rate changes using TX PLL switching with the embedded streamer in Arria® 10 devices. |
Reconfigure Arria® 10 Device Transceivers Using Embedded Streamer |
Watch this video to learn how to perform dynamic reconfiguration with the Arria® 10 device transceiver Standard PCS using the embedded streamer. |
Use the IBIS-AMI Model to Estimate Signal Integrity of Arria® 10 Device Transceiver |
Watch this video to learn how to perform a signal integrity simulation with the Arria® 10 device transceiver IBIS-AMI model in the Advanced Link Analyzer. Additionally, this video covers eye diagram reporting. |
7. Debug
Tools
Agilex™ 7 F-Series Device and Stratix® 10 Device E-Tile Channel Placement Tool
Agilex™ 5 Device Clocking and Datapath Tool
Agilex™ 5 Device TX Equalizer Tool
Agilex™ 3 Device Clocking and Datapath Tool
Agilex™ 3 Device TX Equalizer Tool
Stratix® 10 Device E-Tile Transceiver Debug Tool
The debug tool consists of two sub-tools
- Status tool enables you to read and reset PMA parameters and log it in a file. It also enables you to perform adaptation flow (Internal/external loopback, initial adaptation), read and reset bit errors.
- Tuning tool enables you to tune the transceiver with base line PMA parameter configurations for 10Gbps/28Gbps/56Gbps and with custom parameters it enables you to sweep PMA parameters and log it in a file. Use this tool to analyze the health of the transceiver channels in your Stratix® 10 Device E-Tile.
Stratix® 10 Device L-Tile/H-Tile Transceiver PHY Debug Tool
This debug tool consists of four sub-tools:
- Voltage tool enables you to measure the voltage at the receiver data sampling node and transmitter node
- Channel Status tool enables you to check the status locked to data of receiver clock data recovery (CDR), calibration status, loopback status and PRBS generator/checker status
- Adaptation status tool enables you to cross verify the configured adaptation registered bits against the golden bit settings -Golden bits are the recommended bit settings for a given register
- Eye debug tool enables you to measure the eye height and/or eye width
Use this tool to analyze the health of the transceiver channels in your Stratix® 10 Device L-Tile/H-Tile
Arria® 10 Device Transceiver PHY - Fault Tree Analyzer
This interactive fault tree analyzer provides guidelines for troubleshooting issues you may encounter while using Arria® 10 Device Transceiver PHY. The analyzer consists of three sections:
- Native PHY Debug
- Link Tuning Debug
- Dynamic Reconfiguration Debug
Use this fault tree analyzer to help you resolve Transceiver PHY issues and bring up your design as efficiently as possible. Use it along with the Arria® 10 Device Transceiver PHY Debug Tool
Arria® 10 Device Transceiver PHY Debug Tool
This debug tool consists of the same four sub-tools as the Stratix® 10 version:
- Voltage tool enables you to measure the voltage at the receiver data sampling node and transmitter node
- Channel Status tool enables you to check the status locked to data of receiver clock data recovery (CDR), calibration status, loopback status and PRBS generator/checker status
- Adaptation status tool enables you to cross verify the configured adaptation registered bits against the golden bit settings -Golden bits are the recommended bit settings for a given register
- Eye debug tool enables you to measure the eye height and/or eye width
Use this tool to analyze the health of the transceiver channels in your Arria® 10 Device.
Additional Resources
Topic | Agilex™ 7 | Agilex™ 5 | Agilex™ 3 | Quartus® Prime1 |
Stratix® 10 | Arria® 10 | Cyclone® 10 |
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Intellectual Property (IP) Core Release Notes |
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FPGA Device Errata | |||||||
User Guides (Refer to the chapter on debug functions in the following user guides) |
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Transceiver Registers Mapping Guide |
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Notes:
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Explore Other Developer Centers
For other design guidelines, visit the following Developer Centers:
- Board Developer Center - Contains detailed guidelines and considerations for high-speed PCB designs with Altera® FPGAs and SoC FPGAs.
- Embedded Software Developer Center - Contains guidance on how to design in an embedded environment with SoC FPGAs.
- FPGA Developer Center - Contains resources to complete your Altera® FPGA design.