Transceiver PHY IP Support Center

Welcome to the Transceiver PHY IP support center!

Here you will find information on how to select, design, and implement transceiver links. There are also guidelines on how to bring up your system and debug the transceiver links. This page is organized into categories that align with a high-speed transceiver system design flow from start to finish.

Enjoy your journey!

Get support resources for Intel® Agilex™, Intel® Stratix® 10, Intel® Arria® 10, and Intel® Cyclone® 10 devices from the pages below. For other devices, search from the following links: Training Course Videos, Webcasts Design Examples, and Knowledge Base.

Getting Started

What's New

• Intel Agilex device datasheet ›
• E-Tile transceiver PHY user guide ›
• AN 886: Intel Agilex device design guidelines ›

1. Device and IP Selection

Which Intel® FPGA Device Family Should I Use?

1. The values shown in the table above are for standard power modes. In reduced power mode, the maximum data rate for Intel Arria® 10 GX device channels (chip-to-chip) is 11.3 Gbps. As the GT transceiver channels are designed for peak performance, they do not have a reduced power mode of operation. To operate GX transceiver channels at designated data rates in standard and reduced power modes, apply the corresponding core and periphery power supplies. For more details, refer to the Intel Arria 10 Device Datasheet.
2. Intel Arria 10 and Intel Stratix 10 device transceivers can support data rates below 1.0 Gbps through over sampling.
3. For SX and GX device variants, the maximum transceiver data rates are specified for the fastest (–1) transceiver speed grade. Refer to the Device Datasheet for lower speed grade specifications.
4. For GT device variants, the maximum transceiver data rates are specified for (-1) transceiver speed grade. Refer to the Device Datasheet for the lower speed grade specifications.
5. Intel Stratix 10 device transceivers have both GX and GXT types of transceiver channels. For details, refer to the Intel Stratix 10 L-/H-Tile Transceiver PHY User Guide.
6. SR-IOV stands for Single-Root Input Output Virtualization.
7. Intel Arria 10 and Intel Stratix 10 device transceivers can support data rates below 1.0 Gbps through over sampling.
8. Backplane applications refer to the ones that require advanced equalization, such as decision feedback equalization (DFE) enabled to compensate for channel loss.

Intel FPGA Device Datasheets

• Intel Agilex device datasheet ›
• Intel Stratix 10 device datasheet ›
• Intel Cyclone® 10 GX device datasheet ›
• Intel Arria 10 device datasheet ›

Additional Resources

Refer to the Overview chapter of the following user guides:

Intel Agilex Devices

• E-Tile transceiver PHY user guide ›

Intel Stratix 10 Devices

• Intel Stratix 10 L- and H-Tile transceiver PHY user guide ›
• E-Tile transceiver PHY user guide ›
• AN 778 - Intel Stratix 10 transceiver usage ›

Intel Cyclone 10 Devices

• Intel Cyclone 10 transceiver PHY user guide ›

Intel Arria 10 Devices

• Intel Arria 10 transceiver PHY user guide ›

2. Design Flow and IP Integration

Where Can I Find Information on Transceiver Usage?

• AN 778: Intel Stratix 10 transceiver usage ›
• E-Tile channel placement tool ›

Use the E-Tile Channel Placement Tool in conjunction with the Intel Stratix 10 Device Family Pin Connection Guidelines, to swiftly plan protocol placements in the E-Tile prior to reading comprehensive documentation and implementing designs in the Intel® Quartus® Prime software. The Excel-based E-Tile Channel Placement Tool is supplemented with instruction, legend, revision, and protocols tabs.

What Design Recommendations Should I Consider?

Intel Agilex Devices

• AN 886: Intel Agilex device design guidelines ›

Intel Stratix 10 Devices

• Intel Stratix 10 device design guidelines ›

Intel Cyclone 10 Devices

• Intel Cyclone 10 GX device errata and design guidelines ›

Intel Arria 10 Devices

• Intel Arria 10 GX/GT device errata and design recommendations ›
• Intel Arria® 10 SX device errata and design recommendation ›

Where Can I Find Information on Transceiver PHY IP Integration?

Intel Agilex Devices

• E-Tile transceiver PHY user guide ›
• Intel Agilex clocking and PLL user guide ›

Intel Stratix 10 Devices

• Intel Stratix 10 L- and H-Tile transceiver PHY user guide ›
• E-Tile transceiver PHY user guide ›

Intel Cyclone 10 Devices

• Intel Cyclone 10 transceiver PHY user guide ›
• AN 801: Intel Cyclone 10 device design guidelines ›

Intel Arria 10 Devices

• Intel Arria 10 transceiver PHY user guide ›
• AN 738: Intel Arria 10 device design guidelines ›

Where Can I Find Information on the Transceiver PHY IP Register Mapping?

Intel Stratix 10 Devices

• Logical view of the Intel Stratix 10 L- and H-Tile transceiver registers ›

Intel Cyclone 10 Devices

• Logical view of the Intel Cyclone 10 transceiver registers ›

Intel Arria 10 Devices

• Logical view of the Intel Arria 10 transceiver registers ›

Analog Settings Guidelines

Intel Stratix 10 Devices

• Intel Stratix 10 L-Tile/H-Tile pre-emphasis and output swing sstimator ›

Intel Cyclone 10 and Intel Arria 10 Devices

• Intel Cyclone 10 and Intel Arria 10 pre-emphasis and output swing estimator ›

Additional Resources

• Intel Arria 10 transceiver PHY pin planning (FPGA Wiki) ›

3. Board Design and Power Management

Board Design Guidelines

• Intel Agilex configuration user guide ›
• Intel Agilex device family high-speed serial interface signal integrity design guidelines ›
• AN 672: Transceiver link design guidelines for high- Gbps data rate transmission ›
• AN 114: Board design guidelines for Intel® Programmable device packages ›
• AN 766: Intel Stratix 10 devices, high-speed signal interface layout design guideline ›
• AN 613: PCB stackup design considerations for Intel FPGAs ›

Pin Connection Guidelines

Intel Agilex Devices

• Intel Agilex device family pin connection guidelines ›

Intel Stratix 10 Devices

• Intel Stratix 10 device family pin connection guidelines ›

Intel Cyclone 10 Devices

• ntel Cyclone 10 GX device family pin connection guidelines ›

Intel Arria 10 Devices

• Intel Arria 10 GX, GT, and SX device family pin connection guidelines ›

Schematic Review

Intel Agilex Devices

• Intel Agilex schematic review worksheet ›

Intel Stratix 10 Devices

• Intel Stratix 10 GX, MX, and SX schematic review worksheet ›

Intel Cyclone 10 Devices

• Intel Cyclone 10 GX schematic review worksheet ›

Intel Arria 10 Devices

• Intel Arria 10 GX, GT, and SX schematic review worksheet ›

Power Management

• Intel Agilex power management user guide ›
• Early Power Estimator (EPE) and power analyzer ›
• AN 692 Power sequencing considerations for Intel Cyclone 10 GX, Intel Arria 10, Intel Stratix 10 and Intel Agilex devices ›
• AN 750: Using the Intel FPGA PDN tool to optimize your power delivery network design ›
• Device-Specific Power Deliver Network (PDN) tool 2.0 user guide ›

Simulation Models & Tools

Intel ® Advanced Link Analyzer ›

The Intel® Advanced Link Analyzer is a state-of-the art jitter/noise eye link analysis tool that allows you to quickly and easily evaluate high-speed serial link performance. It is an ideal pre-design tool to help you understand how Intel FPGA solutions can fit your system requirements. It is also an effective tool for post-design support to assist in debug and validation.

Models

• IBIS AMI models ›
• HSPICE models ›

Development Kit User Guides

Intel Agilex Devices

• Intel Agilex F-Series FPGA development kit ›
• Intel Agilex transceiver-SoC development kit ›

Intel Stratix 10 Devices

• Intel Stratix 10 development kit user guide ›
• Intel Stratix10 GX transceiver signal integrity development kit user guide ›

Intel Arria 10 Devices

• Intel Arria 10 development kit user guide ›
• Intel Arria 10 SoC development kit user guide ›
• Intel Arria 10 GX transceiver signal integrity development kit user guide ›

4. Interoperability and Standards Testing

Applications

• Intel Agilex General Purpose I/O and LVDS SERDES user guide ›
• AN 835: PAM4 signaling fundamentals ›
• AN 846: Intel Stratix 10 forward error correction ›

Models

• IEEE 1149.6 BSDL files ›

5. Design Examples and Reference Designs

Design Examples and Reference Designs

Intel Agilex Devices

• High-Speed Transceiver Demo Designs - Intel® Agilex® Device I-Series with F-Tile
• High-Speed Transceiver Demo Designs - Intel® Agilex® Device F-series (E-Tile)

Intel Stratix 10 Devices

• High-speed transceiver demo designs - Stratix 10 TX Series ›
• High-speed transceiver demo designs - Stratix 10 GX Series ›

Intel Cyclone 10 Devices

• Intel Cyclone 10 transceiver PHY basic design examples (Intel Community) ›

Intel Arria 10 Devices

• Terasic DE10 advanced with Intel Arria 10 SoC board ›
• ACHILLES instant development kit with Intel Arria 10 FPGA SoM starter board ›
• Intel Arria 10 transceiver PHY design examples (Intel Community) ›
• Intel Arria 10 transceiver PHY basic design examples (Intel Community) ›
• High-speed transceiver demo designs - Intel Arria 10 Series ›

6. Training Courses and Videos

Recommended Training Courses

Other Training Courses

• Transceiver training courses ›

Recommended Videos

Other Videos

7. Debug

Tools

Intel Stratix 10 Device E-Tile Transceiver Debug Tool

The debug tool consists of two sub-tools

1. Status tool enables you to read and reset PMA parameters and log it in a file. It also enables you to perform adaptation flow (Internal/external loopback, initial adaptation), read and reset bit errors.
2. Tuning tool enables you to tune the transceiver with base line PMA parameter configurations for 10Gbps/28Gbps/56Gbps and with custom parameters it enables you to sweep PMA parameters and log it in a file. Use this tool to analyze the health of the transceiver channels in your Intel Stratix 10 Device E-Tile.

• Download user guide ›

Intel Stratix 10 Device L-Tile/H-Tile Transceiver PHY Debug Tool

This debug tool consists of four sub-tools:

1. Voltage tool enables you to measure the voltage at the receiver data sampling node and transmitter node
2. Channel Status tool enables you to check the status locked to data of receiver clock data recovery (CDR), calibration status, loopback status and PRBS generator/checker status
3. Adaptation status tool enables you to cross verify the configured adaptation registered bits against the golden bit settings -Golden bits are the recommended bit settings for a given register
4. Eye debug tool enables you to measure the eye height and/or eye width

Use this tool to analyze the health of the transceiver channels in your Intel Stratix 10 Device L-Tile/H-Tile

• Download tool tutorial ›

Intel Arria 10 Device Transceiver PHY - Fault Tree Analyzer

This interactive fault tree analyzer provides guidelines for troubleshooting issues you may encounter while using Intel Arria 10 Device Transceiver PHY. The analyzer consists of three sections:

1. Native PHY Debug
2. Link Tuning Debug
3. Dynamic Reconfiguration Debug

Use this fault tree analyzer to help you resolve Transceiver PHY issues and bring up your design as efficiently as possible. Use it along with the Intel Arria 10 Device Transceiver PHY Debug Tool

• Download user guide ›

Intel Arria 10 Device Transceiver PHY Debug Tool

This debug tool consists of the same four sub-tools as the Intel Stratix 10 version:

1. Voltage tool enables you to measure the voltage at the receiver data sampling node and transmitter node
2. Channel Status tool enables you to check the status locked to data of receiver clock data recovery (CDR), calibration status, loopback status and PRBS generator/checker status
3. Adaptation status tool enables you to cross verify the configured adaptation registered bits against the golden bit settings -Golden bits are the recommended bit settings for a given register
4. Eye debug tool enables you to measure the eye height and/or eye width

Use this tool to analyze the health of the transceiver channels in your Intel Arria 10 Device

• Tool Tutorial - Coming soon! ›
• Refer to the relevant Intel Stratix 10 device tutorial ›

Intellectual Property (IP) Core Release Notes

Intel® Quartus® Prime Design Suite Release Notes (note: Transceiver Native PHY IP Release Notes are now found within Intel® Quartus® Prime Design Suite Release Notes)

• Issues addressed in version 18.0 ›
• Issues addressed in version 17.1 update 1 ›
• Issues addressed in version 17.1 update 2 ›

Intel FPGA Device Errata

Intel Stratix 10 Devices

• Intel Stratix 10 GX L-Tile production device errata ›
• Intel Stratix 10 SX production device errata ›

Intel Cyclone 10 Devices

• Intel Cyclone 10 GX device errata and design guidelines ›

Intel Arria 10 Devices

• Intel Arria 10 GX/GT device errata and design recommendations ›
• Intel Arria 10 SX device errata and design recommendations ›

User Guides

Refer to the chapter on Debug Functions in the following user guides:

Intel Agilex Devices

• E-Tile transceiver PHY user guide ›

Intel Stratix 10 Devices

• Intel Stratix 10 L- and H-Tile transceiver PHY user guide ›
• E-Tile transceiver PHY user guide ›

Intel Cyclone 10 Devices

• Intel Cyclone 10 transceiver PHY user guide ›

Intel Arria 10 Devices

• Intel Arria 10 transceiver PHY user guide ›

Knowledge Base Solution

• Search the knowledge base (Intel Agilex devices) ›
• Search the knowledge base (Intel Stratix 10 devices) ›
• Search the knowledge base (Intel Cyclone 10 devices) ›
• Search the knowledge base (Intel Arria 10 devices) ›

Transceiver Registers Mapping Guide

Intel Stratix 10 Devices

• Logical View of the Intel Stratix 10 L- and H-Tile Transceiver Registers ›

Intel Cyclone 10 Devices

• Logical View of the Intel Cyclone 10 Transceiver Registers ›

Intel Arria 10 Devices

• Logical View of the Intel Arria 10 Transceiver Registers ›

Additional Resources

• Intel® Quartus® Prime Standard Edition Handbook Volume 3: Verification (Chapter: Debugging Transceiver Links) ›
• Intel® Quartus® Prime Pro Edition Handbook Volume 3: Verification (Chapter: Debugging Transceiver Links) ›