Agilex™ 7 FPGAs and SoCs Device Data Sheet: F-Series and I-Series

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ID 683301
Date 12/06/2024
Public
Document Table of Contents
Document Table of Contents x
Agilex™ 7 FPGAs and SoCs Device Data Sheet: F-Series and I-Series
Agilex™ 7 FPGAs and SoCs Device Data Sheet: F-Series and I-Series x
Electrical Characteristics Switching Characteristics Configuration Specifications I/O Timing Programmable IOE Delay Glossary Document Revision History for the Agilex 7 FPGAs and SoCs Device Data Sheet: F-Series and I-Series
Electrical Characteristics x
Operating Conditions
Operating Conditions x
Absolute Maximum Ratings Maximum Allowed Overshoot and Undershoot Voltage Recommended Operating Conditions DC Characteristics I/O Standard Specifications
Recommended Operating Conditions x
Recommended Operating Conditions E-Tile Transceiver Power Supply Recommended Operating Conditions P-Tile Transceiver Power Supply Recommended Operating Conditions R-Tile Transceiver Power Supply Recommended Operating Conditions F-Tile Transceiver Power Supply Recommended Operating Conditions HPS Power Supply Recommended Operating Conditions
DC Characteristics x
Supply Current and Power Consumption I/O Pin Leakage Current Bus Hold Specifications OCT Calibration Accuracy Specifications OCT Without Calibration Resistance Tolerance Specifications Pin Capacitance Internal Weak Pull-Up Resistor Hysteresis Specifications for Schmitt Trigger Input
I/O Standard Specifications x
Single-Ended I/O Standards Specifications Single-Ended SSTL, HSTL, HSUL, and POD I/O Reference Voltage Specifications Single-Ended SSTL, HSTL, HSUL, and POD I/O Standards Signal Specifications Differential SSTL, HSTL, and HSUL I/O Standards Specifications Differential POD I/O Standards Specifications Differential I/O Standards Specifications
Switching Characteristics x
Core Performance Specifications Periphery Performance Specifications E-Tile Transceiver Performance Specifications P-Tile Transceiver Performance Specifications R-Tile Transceiver Performance Specifications F-Tile Transceiver Performance Specifications HPS Performance Specifications
Core Performance Specifications x
Clock Tree Specifications I/O PLL Specifications DSP Block Specifications Memory Block Specifications Local Temperature Sensor Specifications Remote Temperature Diode Specifications Voltage Sensor Specifications
Periphery Performance Specifications x
LVDS SERDES Specifications DPA Lock Time Specifications LVDS SERDES Soft-CDR Sinusoidal Jitter Tolerance Specifications Memory Standards Supported DLL Range Specifications Memory Output Clock Jitter Specifications
E-Tile Transceiver Performance Specifications x
E-Tile Transceiver Performance E-Tile Transceiver Reference Clock Specifications E-Tile Transmitter Specifications E-Tile Receiver Specifications
P-Tile Transceiver Performance Specifications x
P-Tile Transceiver Performance P-Tile Transceiver Reference Clock Specifications P-Tile Transmitter Specifications P-Tile Receiver Specifications
R-Tile Transceiver Performance Specifications x
R-Tile Transceiver Performance R-Tile Transceiver Reference Clock Specifications R-Tile Transmitter Specifications R-Tile Receiver Specifications
F-Tile Transceiver Performance Specifications x
F-Tile Transceiver Performance F-Tile Transceiver Reference Clock Specifications F-Tile Transmitter Specifications F-Tile Receiver Specifications F-Tile Electrical Compliance
HPS Performance Specifications x
HPS Clock Performance HPS Internal Oscillator Frequency HPS PLL Specifications HPS Cold Reset HPS SPI Timing Characteristics HPS SD/MMC Timing Characteristics HPS USB UPLI Timing Characteristics HPS Ethernet Media Access Controller (EMAC) Timing Characteristics HPS I2C Timing Characteristics HPS NAND Timing Characteristics HPS Trace Timing Characteristics HPS GPIO Interface HPS JTAG Timing Characteristics HPS Programmable I/O Timing Characteristics
Configuration Specifications x
General Configuration Timing Specifications POR Specifications External Configuration Clock Source Requirements JTAG Configuration Timing AS Configuration Timing Avalon® Streaming (Avalon®-ST) Configuration Timing Configuration Bit Stream Sizes
Agilex™ 7 FPGAs and SoCs Device Data Sheet: F-Series and I-Series

Agilex™ 7 FPGAs and SoCs Device Data Sheet: F-Series and I-Series

This data sheet describes the electrical characteristics, switching characteristics, configuration specifications, and timing.

Until the data sheet status for a device reaches Final, the specifications are subject to change at any time and at Intel's discretion.

Table 1.  Data Sheet Status for Agilex™ 7 FPGAs and SoCs F-Series
Device Tile Package Status
AGF 012/014 E-Tile and P-Tile R24A Final
AGF 012/014 E-Tile and P-Tile R24B Final
AGF 019/022/023/027 E-Tile and P-Tile R25A Final
AGF 006/008 F-Tile R16A Preliminary
AGF 006/008/012/014/019/022/023/027 F-Tile R24C Preliminary
AGF 019/022/023/027 F-Tile R31C Preliminary
AGF 006/008/012/014 F-Tile R24D Preliminary
Table 2.  Data Sheet Status for Agilex™ 7 FPGAs and SoCs I-Series
Device Tile Package Status
AGI 019/023 R-Tile and F-Tile R18A Preliminary
AGI 022/027 R-Tile and F-Tile R29A Preliminary
AGI 022/027 R-Tile and F-Tile R31A Preliminary
AGI 019/022/023/027 F-Tile R31B Preliminary
AGI 035/040 F-Tile R39A Preliminary
AGI 041 R-Tile and F-Tile R29D Preliminary
AGI 041 F-Tile R31B Preliminary
AGI 041 R-Tile and F-Tile R31E Preliminary
The following descriptors designate the status level currently applicable to the relevant variant:
  • Advance: These are target specifications based on simulation.
  • Preliminary: These specifications are based on simulation, early validation, and/or early characterization data.
  • Final: These are production specifications based on silicon validation and/or characterization.
Table 3.  Device Grades, Core Speed Grades, and Power Options Supported For specification status, see the Data Sheet Status table
Device Grade Speed Grade and Power Option Supported
Extended –E1V (fastest)
–E2V
–E3V
–E3E
–E4X
–E4F
Industrial –I1V
–I2V
–I3V
–I3E
The suffix after the speed grade denotes the power options offered.
  • V—standard power (VID)
  • E—lower power (VID)
  • X—lowest power (VID)
  • F—fixed voltage

Section Content
Electrical Characteristics
Switching Characteristics
Configuration Specifications
I/O Timing
Programmable IOE Delay
Glossary
Document Revision History for the Agilex 7 FPGAs and SoCs Device Data Sheet: F-Series and I-Series

Related Information
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