Intel Agilex® 7 FPGAs and SoCs Device Data Sheet: F-Series and I-Series

ID 683301
Date 12/04/2023
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Maximum Allowed Overshoot and Undershoot Voltage

During transitions, input signals may overshoot to the voltage listed in the following tables and undershoot to –1.1 V when using VCCIO_HPS/ VCCIO_SDM of 1.8 V and –0.3 V when using VCCIO_PIO of 1.2 V for input currents less than 100 mA and periods shorter than 20 ns.

No overshooting beyond 1.7 V and undershooting below 0 V is allowed when using VCCIO_PIO = 1.5 V.

The maximum allowed overshoot duration is specified as a percentage of high time (calculated as ([delta T]/T) × 100) over the lifetime of the device. A DC signal is equivalent to 100% duty cycle.

Table 5.  Maximum Allowed Overshoot During Transitions (for 1.2 V I/O in GPIO Bank)

This table lists the maximum allowed input overshoot voltage and the duration of the overshoot voltage as a percentage of device lifetime.

For specification status, see the Data Sheet Status table

Symbol Description Condition (V) Overshoot Duration as % at TJ = 100°C Unit
Vi (AC) AC input voltage VCCIO_PIO + 0.30 100 %
VCCIO_PIO + 0.35 37 %
VCCIO_PIO + 0.40 9 %
VCCIO_PIO + 0.45 3 %
VCCIO_PIO + 0.50 1 %
> VCCIO_PIO + 0.50 No overshoot allowed %
Table 6.  Maximum Allowed Overshoot During Transitions (for 1.8 V I/O in HPS and SDM I/O Banks)

This table lists the maximum allowed input overshoot voltage and the duration of the overshoot voltage as a percentage of device lifetime.

For specification status, see the Data Sheet Status table

Symbol Description Condition (V) Overshoot Duration as % at TJ = 100°C Unit
Vi (AC) AC input voltage VCCIO_SDM + 0.30, VCCIO_HPS + 0.30 100 %
VCCIO_SDM + 0.35, VCCIO_HPS + 0.35 60 %
VCCIO_SDM + 0.40, VCCIO_HPS + 0.40 30 %
VCCIO_SDM + 0.45, VCCIO_HPS + 0.45 20 %
VCCIO_SDM + 0.50, VCCIO_HPS + 0.50 10 %
VCCIO_SDM + 0.55, VCCIO_HPS + 0.55 6 %
>VCCIO_SDM + 0.55, >VCCIO_HPS + 0.55 No overshoot allowed %

For example, when using 1.2 V I/O standard with 1.26 V VCCIO_PIO, a signal that overshoots to 1.71 V can only be at 1.71 V for ~3% over the lifetime of the device. For an overshoot of 1.56 V, the percentage of high time for the overshoot can be as high as 100% over the lifetime of the device.

Figure 1. Overshoot Duration Example (for 1.2 V GPIO Bank at VCCIO_PIO = 1.26 V)