Agilex™ 7 FPGAs and SoCs Device Data Sheet: F-Series and I-Series

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ID 683301
Date 7/08/2024
Public
Document Table of Contents
Document Table of Contents x
Agilex™ 7 FPGAs and SoCs Device Data Sheet: F-Series and I-Series
Agilex™ 7 FPGAs and SoCs Device Data Sheet: F-Series and I-Series x
Electrical Characteristics Switching Characteristics Configuration Specifications I/O Timing Programmable IOE Delay Glossary Document Revision History for the Agilex 7 FPGAs and SoCs Device Data Sheet: F-Series and I-Series
Electrical Characteristics x
Operating Conditions
Operating Conditions x
Absolute Maximum Ratings Maximum Allowed Overshoot and Undershoot Voltage Recommended Operating Conditions DC Characteristics I/O Standard Specifications
Recommended Operating Conditions x
Recommended Operating Conditions E-Tile Transceiver Power Supply Recommended Operating Conditions P-Tile Transceiver Power Supply Recommended Operating Conditions R-Tile Transceiver Power Supply Recommended Operating Conditions F-Tile Transceiver Power Supply Recommended Operating Conditions HPS Power Supply Recommended Operating Conditions
DC Characteristics x
Supply Current and Power Consumption I/O Pin Leakage Current Bus Hold Specifications OCT Calibration Accuracy Specifications OCT Without Calibration Resistance Tolerance Specifications Pin Capacitance Internal Weak Pull-Up Resistor Hysteresis Specifications for Schmitt Trigger Input
I/O Standard Specifications x
Single-Ended I/O Standards Specifications Single-Ended SSTL, HSTL, HSUL, and POD I/O Reference Voltage Specifications Single-Ended SSTL, HSTL, HSUL, and POD I/O Standards Signal Specifications Differential SSTL, HSTL, and HSUL I/O Standards Specifications Differential POD I/O Standards Specifications Differential I/O Standards Specifications
Switching Characteristics x
Core Performance Specifications Periphery Performance Specifications E-Tile Transceiver Performance Specifications P-Tile Transceiver Performance Specifications R-Tile Transceiver Performance Specifications F-Tile Transceiver Performance Specifications HPS Performance Specifications
Core Performance Specifications x
Clock Tree Specifications I/O PLL Specifications DSP Block Specifications Memory Block Specifications Local Temperature Sensor Specifications Remote Temperature Diode Specifications Voltage Sensor Specifications
Periphery Performance Specifications x
LVDS SERDES Specifications DPA Lock Time Specifications LVDS SERDES Soft-CDR Sinusoidal Jitter Tolerance Specifications Memory Standards Supported DLL Range Specifications Memory Output Clock Jitter Specifications
E-Tile Transceiver Performance Specifications x
E-Tile Transceiver Performance E-Tile Transceiver Reference Clock Specifications E-Tile Transmitter Specifications E-Tile Receiver Specifications
P-Tile Transceiver Performance Specifications x
P-Tile Transceiver Performance P-Tile Transceiver Reference Clock Specifications P-Tile Transmitter Specifications P-Tile Receiver Specifications
R-Tile Transceiver Performance Specifications x
R-Tile Transceiver Performance R-Tile Transceiver Reference Clock Specifications R-Tile Transmitter Specifications R-Tile Receiver Specifications
F-Tile Transceiver Performance Specifications x
F-Tile Transceiver Performance F-Tile Transceiver Reference Clock Specifications F-Tile Transmitter Specifications F-Tile Receiver Specifications F-Tile Electrical Compliance
HPS Performance Specifications x
HPS Clock Performance HPS Internal Oscillator Frequency HPS PLL Specifications HPS Cold Reset HPS SPI Timing Characteristics HPS SD/MMC Timing Characteristics HPS USB UPLI Timing Characteristics HPS Ethernet Media Access Controller (EMAC) Timing Characteristics HPS I2C Timing Characteristics HPS NAND Timing Characteristics HPS Trace Timing Characteristics HPS GPIO Interface HPS JTAG Timing Characteristics HPS Programmable I/O Timing Characteristics
Configuration Specifications x
General Configuration Timing Specifications POR Specifications External Configuration Clock Source Requirements JTAG Configuration Timing AS Configuration Timing Avalon® Streaming (Avalon®-ST) Configuration Timing Configuration Bit Stream Sizes
Agilex™ 7 FPGAs and SoCs Device Data Sheet: F-Series and I-Series

Maximum Allowed Overshoot and Undershoot Voltage

During transitions, input signals may overshoot to the voltage listed in the following tables and undershoot to –1.1 V when using VCCIO_HPS/ VCCIO_SDM of 1.8 V and –0.3 V when using VCCIO_PIO of 1.2 V for input currents less than 100 mA and periods shorter than 20 ns.

No overshooting beyond 1.7 V and undershooting below 0 V is allowed when using VCCIO_PIO = 1.5 V.

The maximum allowed overshoot duration is specified as a percentage of high time (calculated as ([delta T]/T) × 100) over the lifetime of the device. A DC signal is equivalent to 100% duty cycle.

Table 5.  Maximum Allowed Overshoot During Transitions (for 1.2 V I/O in GPIO Bank)

This table lists the maximum allowed input overshoot voltage and the duration of the overshoot voltage as a percentage of device lifetime.

For specification status, see the Data Sheet Status table

Symbol Description Condition (V) Overshoot Duration as % at TJ = 100°C Unit
Vi (AC) AC input voltage VCCIO_PIO + 0.30 100 %
VCCIO_PIO + 0.35 37 %
VCCIO_PIO + 0.40 9 %
VCCIO_PIO + 0.45 3 %
VCCIO_PIO + 0.50 1 %
> VCCIO_PIO + 0.50 No overshoot allowed %
Table 6.  Maximum Allowed Overshoot During Transitions (for 1.8 V I/O in HPS and SDM I/O Banks)

This table lists the maximum allowed input overshoot voltage and the duration of the overshoot voltage as a percentage of device lifetime.

For specification status, see the Data Sheet Status table

Symbol Description Condition (V) Overshoot Duration as % at TJ = 100°C Unit
Vi (AC) AC input voltage VCCIO_SDM + 0.30, VCCIO_HPS + 0.30 100 %
VCCIO_SDM + 0.35, VCCIO_HPS + 0.35 60 %
VCCIO_SDM + 0.40, VCCIO_HPS + 0.40 30 %
VCCIO_SDM + 0.45, VCCIO_HPS + 0.45 20 %
VCCIO_SDM + 0.50, VCCIO_HPS + 0.50 10 %
VCCIO_SDM + 0.55, VCCIO_HPS + 0.55 6 %
>VCCIO_SDM + 0.55, >VCCIO_HPS + 0.55 No overshoot allowed %

For example, when using 1.2 V I/O standard with 1.26 V VCCIO_PIO, a signal that overshoots to 1.71 V can only be at 1.71 V for ~3% over the lifetime of the device. For an overshoot of 1.56 V, the percentage of high time for the overshoot can be as high as 100% over the lifetime of the device.

Figure 1. Overshoot Duration Example (for 1.2 V GPIO Bank at VCCIO_PIO = 1.26 V)
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