Agilex™ 7 FPGAs and SoCs Device Data Sheet: F-Series and I-Series

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ID 683301
Date 8/29/2025
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Document Table of Contents
Document Table of Contents x
Agilex™ 7 FPGAs and SoCs Device Data Sheet: F-Series and I-Series
Agilex™ 7 FPGAs and SoCs Device Data Sheet: F-Series and I-Series x
Electrical Characteristics Switching Characteristics Configuration Specifications I/O Timing Programmable IOE Delay Glossary Document Revision History for the Agilex 7 FPGAs and SoCs Device Data Sheet: F-Series and I-Series
Electrical Characteristics x
Operating Conditions
Operating Conditions x
Absolute Maximum Ratings Maximum Allowed Overshoot and Undershoot Voltage Recommended Operating Conditions DC Characteristics I/O Standard Specifications
Recommended Operating Conditions x
Recommended Operating Conditions E-Tile Transceiver Power Supply Recommended Operating Conditions P-Tile Transceiver Power Supply Recommended Operating Conditions R-Tile Transceiver Power Supply Recommended Operating Conditions F-Tile Transceiver Power Supply Recommended Operating Conditions HPS Power Supply Recommended Operating Conditions
DC Characteristics x
Supply Current and Power Consumption I/O Pin Leakage Current Bus Hold Specifications OCT Calibration Accuracy Specifications OCT Without Calibration Resistance Tolerance Specifications Pin Capacitance Internal Weak Pull-Up Resistor Hysteresis Specifications for Schmitt Trigger Input
I/O Standard Specifications x
Single-Ended I/O Standards Specifications Single-Ended SSTL, HSTL, HSUL, and POD I/O Reference Voltage Specifications Single-Ended SSTL, HSTL, HSUL, and POD I/O Standards Signal Specifications Differential SSTL, HSTL, and HSUL I/O Standards Specifications Differential POD I/O Standards Specifications Differential I/O Standards Specifications
Switching Characteristics x
Core Performance Specifications Periphery Performance Specifications E-Tile Transceiver Performance Specifications P-Tile Transceiver Performance Specifications R-Tile Transceiver Performance Specifications F-Tile Transceiver Performance Specifications HPS Performance Specifications
Core Performance Specifications x
Clock Tree Specifications I/O PLL Specifications DSP Block Specifications Memory Block Specifications Local Temperature Sensor Specifications Remote Temperature Diode Specifications Voltage Sensor Specifications
Periphery Performance Specifications x
LVDS SERDES Specifications DPA Lock Time Specifications LVDS SERDES Soft-CDR Sinusoidal Jitter Tolerance Specifications Memory Standards Supported DLL Range Specifications Memory Output Clock Jitter Specifications
E-Tile Transceiver Performance Specifications x
E-Tile Transceiver Performance E-Tile Transceiver Reference Clock Specifications E-Tile Transmitter Specifications E-Tile Receiver Specifications
P-Tile Transceiver Performance Specifications x
P-Tile Transceiver Performance P-Tile Transceiver Reference Clock Specifications P-Tile Transmitter Specifications P-Tile Receiver Specifications
R-Tile Transceiver Performance Specifications x
R-Tile Transceiver Performance R-Tile Transceiver Reference Clock Specifications R-Tile Transmitter Specifications R-Tile Receiver Specifications
F-Tile Transceiver Performance Specifications x
F-Tile Transceiver Performance F-Tile Transceiver Reference Clock Specifications F-Tile Transmitter Specifications F-Tile Receiver Specifications F-Tile Electrical Compliance
HPS Performance Specifications x
HPS Clock Performance HPS Internal Oscillator Frequency HPS PLL Specifications HPS Cold Reset HPS SPI Timing Characteristics HPS SD/MMC Timing Characteristics HPS USB UPLI Timing Characteristics HPS Ethernet Media Access Controller (EMAC) Timing Characteristics HPS I2C Timing Characteristics HPS NAND Timing Characteristics HPS Trace Timing Characteristics HPS GPIO Interface HPS JTAG Timing Characteristics HPS Programmable I/O Timing Characteristics
Configuration Specifications x
General Configuration Timing Specifications POR Specifications External Configuration Clock Source Requirements JTAG Configuration Timing AS Configuration Timing Avalon® Streaming (Avalon®-ST) Configuration Timing Configuration Bit Stream Sizes
Agilex™ 7 FPGAs and SoCs Device Data Sheet: F-Series and I-Series

LVDS SERDES Specifications

Table 40.  LVDS SERDES Specifications

LVDS serializer/deserializer (SERDES) block supports SERDES factor J = 3 to 10.

DDR registers support SERDES factor J = 1 to 2.

You must calculate the leftover timing margin in the receiver by performing link timing closure analysis. You must consider the board skew margin, transmitter channel-to-channel skew, and receiver sampling margin to determine the leftover timing margin.

For specification status, see the Data Sheet Status table
Parameter Symbol Condition –1 Speed Grade –2 Speed Grade –3 Speed Grade –4 Speed Grade Unit
Min Typ Max Min Typ Max Min Typ Max Min Typ Max
Clock frequency fHSCLK_in (input clock frequency) True Differential I/O Standards Clock boost factor W = 1 to 4050 10 — 800 10 — 700 10 — 625 10 — 625 MHz
fHSCLK_in (input clock frequency) Single-Ended I/O Standards Clock boost factor W = 1 to 4050 10 — 625 10 — 625 10 — 525 10 — 525 MHz
fHSCLK_OUT (output clock frequency) — — — 80051 — — 70051 — — 62551 — — 62551 MHz
Transmitter True Differential I/O Standards - fHSDR (data rate)52 SERDES factor J = 4 to 1053 54 55 150 — 1,600 150 — 1,434 150 — 1,250 150 — 1,000 Mbps
SERDES factor J = 353 54 55 150 — 1,200 150 — 1,076 150 — 938 150 — 600 Mbps
SERDES factor J = 2, uses DDR registers 150 — 84056 150 — 56 150 — 56 150 — 56 Mbps
SERDES factor J = 1, uses DDR registers 150 — 42056 150 — 56 150 — 56 150 — 56 Mbps
tx Jitter - True Differential I/O Standards Total jitter for data rate, 600 Mbps – 1.6 Gbps ≤1,600 Mbps: 160

≤1,434 Mbps: 200

≤1,250 Mbps: 250

≤1,000 Mbps: 300

≤800 Mbps: 320

600 Mbps: 340

 ≤1,434 Mbps: 200

≤1,250 Mbps: 250

≤1,000 Mbps: 300

≤800 Mbps: 320

600 Mbps: 340

 ≤1,250 Mbps: 250

≤1,000 Mbps: 300

≤800 Mbps: 320

600 Mbps: 340

≤1,000 Mbps: 300

≤800 Mbps: 320

600 Mbps: 340

 ps
Total jitter for data rate, < 600 Mbps — — 0.21 — — 0.21 — — 0.21 — — 0.21 UI
tDUTY 57 TX output clock duty cycle for Differential I/O Standards 45 50 55 45 50 55 45 50 55 45 50 55 %
tRISE & tFALL 54 58 True Differential I/O Standards — — 160 — — 180 — — 200 — — 220 ps
TCCS 52 57 True Differential I/O Standards — — 330 — — 330 — — 330 — — 330 ps
Receiver True Differential I/O Standards - fHSDRDPA (data rate) SERDES factor J = 4 to 1053 54 55 150 — 1,600 150 — 1,434 150 — 1,250 150 — 1,000 Mbps
SERDES factor J = 353 54 55 150 — 1,200 150 — 1,076 150 — 938 150 — 600 Mbps
fHSDR (data rate) (without DPA)52 SERDES factor J = 3 to 10 55 — 59 55 — 59 55 — 59 55 — 59 Mbps
SERDES factor J = 2, uses DDR registers 55 — 56 55 — 56 55 — 56 55 — 56 Mbps
SERDES factor J = 1, uses DDR registers 55 — 56 55 — 56 55 — 56 55 — 56 Mbps
DPA (FIFO mode) DPA run length — — — 10,000 — — 10,000 — — 10,000 — — 10,000 UI
DPA (soft CDR mode) DPA run length SGMII/GbE protocol — — 5 — — 5 — — 5 — — 5 UI
All other protocols — — 50 data transition per 208 UI — — 50 data transition per 208 UI — — 50 data transition per 208 UI — — 50 data transition per 208 UI —
Soft CDR mode Soft-CDR ppm tolerance — –300 — 300 –300 — 300 –300 — 300 –300 — 300 ppm
Non DPA mode Sampling Window — — — 330 — — 330 — — 330 — — 330 ps
50 Clock Boost Factor (W) is the ratio between the input data rate and the input clock rate.
51 This is achieved by using the PHY clock network.
52 Requires package skew compensation with PCB trace length.
53 The Fmax specification is based on the fast clock used for serial data. The interface Fmax is also dependent on the parallel clock domain which is design dependent and requires timing analysis.
54 The VCC and VCCP must be on a combined power layer and a maximum load of 5 pF for chip-to-chip interface.
55 The minimum specification depends on the clock source (for example, the PLL and clock pin) and the clock routing resource that you use. The I/O differential buffer and serializer do not have a minimum toggle rate.
56 The maximum ideal data rate is the SERDES factor (J) × the PLL maximum output frequency (fOUT) provided you can close the design timing and the signal integrity meets the interface requirements.
57 Not applicable for DIVCLK = 1.
58 This applies to default pre-emphasis and VOD settings only.
59 You can estimate the achievable maximum data rate for non-DPA mode by performing link timing closure analysis. You must consider the board skew margin, transmitter delay margin, and receiver sampling margin to determine the maximum data rate supported.
Level Two Title