Agilex™ 7 FPGAs and SoCs Device Data Sheet: F-Series and I-Series

ID 683301
Date 12/06/2024
Public
Document Table of Contents

LVDS SERDES Specifications

Table 40.  LVDS SERDES Specifications

LVDS serializer/deserializer (SERDES) block supports SERDES factor J = 3 to 10.

DDR registers support SERDES factor J = 1 to 2.

You must calculate the leftover timing margin in the receiver by performing link timing closure analysis. You must consider the board skew margin, transmitter channel-to-channel skew, and receiver sampling margin to determine the leftover timing margin.

For specification status, see the Data Sheet Status table

Parameter Symbol Condition –1 Speed Grade –2 Speed Grade –3 Speed Grade –4 Speed Grade Unit
Min Typ Max Min Typ Max Min Typ Max Min Typ Max
Clock frequency fHSCLK_in (input clock frequency) True Differential I/O Standards Clock boost factor W = 1 to 4049 10 800 10 700 10 625 10 625 MHz
fHSCLK_in (input clock frequency) Single-Ended I/O Standards Clock boost factor W = 1 to 4049 10 625 10 625 10 525 10 525 MHz
fHSCLK_OUT (output clock frequency) 80050 70050 62550 62550 MHz
Transmitter True Differential I/O Standards - fHSDR (data rate)51 SERDES factor J = 4 to 1052 53 54 150 1,600 150 1,434 150 1,250 150 1,000 Mbps
SERDES factor J = 352 53 54 150 1,200 150 1,076 150 938 150 600 Mbps
SERDES factor J = 2, uses DDR registers 150 84055 150 55 150 55 150 55 Mbps
SERDES factor J = 1, uses DDR registers 150 42055 150 55 150 55 150 55 Mbps
tx Jitter - True Differential I/O Standards Total jitter for data rate, 600 Mbps – 1.6 Gbps ≤1,600 Mbps: 160

≤1,434 Mbps: 200

≤1,250 Mbps: 250

≤1,000 Mbps: 300

≤800 Mbps: 320

600 Mbps: 340

≤1,434 Mbps: 200

≤1,250 Mbps: 250

≤1,000 Mbps: 300

≤800 Mbps: 320

600 Mbps: 340

≤1,250 Mbps: 250

≤1,000 Mbps: 300

≤800 Mbps: 320

600 Mbps: 340

≤1,000 Mbps: 300

≤800 Mbps: 320

600 Mbps: 340

ps
Total jitter for data rate, < 600 Mbps 0.21 0.21 0.21 0.21 UI
tDUTY 56 TX output clock duty cycle for Differential I/O Standards 45 50 55 45 50 55 45 50 55 45 50 55 %
tRISE & tFALL 53 57 True Differential I/O Standards 160 180 200 220 ps
TCCS 51 56 True Differential I/O Standards 330 330 330 330 ps
Receiver True Differential I/O Standards - fHSDRDPA (data rate) SERDES factor J = 4 to 1052 53 54 150 1,600 150 1,434 150 1,250 150 1,000 Mbps
SERDES factor J = 352 53 54 150 1,200 150 1,076 150 938 150 600 Mbps
fHSDR (data rate) (without DPA)51 SERDES factor J = 3 to 10 54 58 54 58 54 58 54 58 Mbps
SERDES factor J = 2, uses DDR registers 54 55 54 55 54 55 54 55 Mbps
SERDES factor J = 1, uses DDR registers 54 55 54 55 54 55 54 55 Mbps
DPA (FIFO mode) DPA run length 10,000 10,000 10,000 10,000 UI
DPA (soft CDR mode) DPA run length SGMII/GbE protocol 5 5 5 5 UI
All other protocols 50 data transition per 208 UI 50 data transition per 208 UI 50 data transition per 208 UI 50 data transition per 208 UI
Soft CDR mode Soft-CDR ppm tolerance –300 300 –300 300 –300 300 –300 300 ppm
Non DPA mode Sampling Window 330 330 330 330 ps
49 Clock Boost Factor (W) is the ratio between the input data rate and the input clock rate.
50 This is achieved by using the PHY clock network.
51 Requires package skew compensation with PCB trace length.
52 The Fmax specification is based on the fast clock used for serial data. The interface Fmax is also dependent on the parallel clock domain which is design dependent and requires timing analysis.
53 The VCC and VCCP must be on a combined power layer and a maximum load of 5 pF for chip-to-chip interface.
54 The minimum specification depends on the clock source (for example, the PLL and clock pin) and the clock routing resource that you use. The I/O differential buffer and serializer do not have a minimum toggle rate.
55 The maximum ideal data rate is the SERDES factor (J) × the PLL maximum output frequency (fOUT) provided you can close the design timing and the signal integrity meets the interface requirements.
56 Not applicable for DIVCLK = 1.
57 This applies to default pre-emphasis and VOD settings only.
58 You can estimate the achievable maximum data rate for non-DPA mode by performing link timing closure analysis. You must consider the board skew margin, transmitter delay margin, and receiver sampling margin to determine the maximum data rate supported.