Intel® Agilex™ F-Series and I-Series Device Data Sheet

ID 683301
Date 12/19/2022
Public
Document Table of Contents

I/O PLL Specifications

Table 30.  I/O PLL Specifications For specification status, see the Data Sheet Status table
Symbol Parameter Condition Min Typ Max Unit
fIN Input clock frequency –1V 10 1,10031 MHz
–2V 10 90031 MHz
–3V, –3E 10 75031 MHz
–4F, –4X 10 65031 MHz
fINPFD Input clock frequency to the PFD 10 325 MHz
fVCO I/O PLL VCO operating range –1V 600 1,600 MHz
–2V 600 1,434 MHz
–3V, –3E 600 1,250 MHz
–4F, –4X 600 1,067 MHz
fCLBW I/O PLL closed-loop bandwidth I/O bank I/O PLL 0.5 10 MHz
Fabric-feeding I/O PLL 1 10 MHz
tEINDUTY Input clock or external feedback clock input duty cycle 40 60 %
fOUT Output frequency for internal clock (C counter) –1V 1,100 MHz
–2V 900 MHz
–3V, –3E 750 MHz
–4F, –4X 650 MHz
fOUT_EXT Output frequency for external clock output –1V 800 MHz
–2V 717 MHz
–3V, –3E 625 MHz
–4F, –4X 500 MHz
tOUTDUTY Duty cycle for dedicated external clock output (when set to 50%) fOUT_EXT < 300 MHz 45 50 55 %
fOUT_EXT ≥ 300 MHz 40/45 32 50 55 32/60 %
tFCOMP 33 External feedback clock compensation time 5 ns
fDYCONFIGCLK Dynamic configuration clock for mgmt_clk 100 MHz
tLOCK Time required to lock from end-of-device configuration or deassertion of areset 1 ms
tDLOCK Time required to lock dynamically (after switchover or reconfiguring any non-post-scale counters/delays) 1 ms
tPLL_PSERR Accuracy of PLL phase shift ±50 ps
tARESET Minimum pulse width on the areset signal 10 ns
tINCCJ Input clock cycle-to-cyle jitter fREF < 100 MHz 34 750 ps (p-p)
fREF ≥ 100 MHz 34 0.15 UI (p-p)
tREFPJ Reference phase jitter (rms)35 Carrier frequency: 100 MHz with integrated bandwidth of 10 kHz to 50 MHz 1.42 ps
tREFPN Reference phase noise36 35 10 Hz –90 dBc/Hz
100 Hz –100 dBc/Hz
1 kHz –110 dBc/Hz
10 kHz –120 dBc/Hz
100 kHz –130 dBc/Hz
1 MHz –138 dBc/Hz
10 MHz –142 dBc/Hz
100 MHz –144 dBc/Hz
tOUTPJ_DC 33 37 Period jitter for dedicated clock output fOUT < 100 MHz 34 17.5 mUI (p-p)
fOUT ≥ 100 MHz 34 175 ps (p-p)
tOUTCCJ_DC 33 37 Cycle-to-cycle jitter for dedicated clock output fOUT < 100 MHz 34 17.5 mUI (p-p)
fOUT ≥ 100 MHz 34 175 ps (p-p)
tOUTPJ_IO 38 37 Period jitter for clock output on the regular I/O fOUT < 100 MHz 34 60 mUI (p-p)
fOUT ≥ 100 MHz 34 600 ps (p-p)
tOUTCCJ_IO 38 37 Cycle-to-cycle jitter for clock output on the regular I/O fOUT < 100 MHz 34 60 mUI (p-p)
fOUT ≥ 100 MHz 34 600 ps (p-p)
tCASC_OUTPJ_DC 33 Period jitter for dedicated clock output in cascaded PLLs fOUT < 100 MHz 34 17.5 mUI (p-p)
fOUT ≥ 100 MHz 34 175 ps (p-p)
31 This specification is limited by the I/O maximum frequency. The maximum achievable I/O frequency is different for each I/O standard and is dependent on design and system specific factors. Ensure proper timing closure in your design and perform HSPICE/IBIS simulations based on your specific design and system setup to determine the maximum achievable frequency in your system.
32 To achieve 5% duty cycle for fOUT_EXT ≥ 300 MHz, you only can use tx_outclk port from the LVDS SERDES Intel® FPGA IP. Refer to the Intel® Agilex™ Clocking and PLL User Guide for the detail design guidelines.
33 Not applicable for fabric-feeding I/O PLL.
34 fREF is fIN/N, specification applies when N = 1.
35 Requirement for Advanced Interface Bus (AIB), High Bandwidth Memory (HBM) Interface, Mobile Industry Processor Interface (MIPI), DDR4 protocol, and LVDS applications only.
36 The phase noise numbers in the table above are the maximum acceptable phase noise values measured at a carrier frequency of 100 MHz. To calculate the phase noise requirement at any other frequency, use the formula: REFCLK phase noise at f (MHz) = REFCLK phase noise at 100 MHz + (20 × log10 (f/100)).
37 This jitter specification does not include the effect of spread-spectrum clock. The magnitude of jitter deterioration is largely depend on the spread-spectrum clock profile used. Refer to the Intel® Agilex™ Clocking and PLL User Guide for the recommended spread-spectrum clock profile.
38 External memory interface clock output jitter specifications use a different measurement method, which are available in the Memory Output Clock Jitter Specifications table.

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