Agilex™ 7 FPGAs and SoCs Device Data Sheet: F-Series and I-Series

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ID 683301
Date 8/29/2025
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Document Table of Contents
Document Table of Contents x
Agilex™ 7 FPGAs and SoCs Device Data Sheet: F-Series and I-Series
Agilex™ 7 FPGAs and SoCs Device Data Sheet: F-Series and I-Series x
Electrical Characteristics Switching Characteristics Configuration Specifications I/O Timing Programmable IOE Delay Glossary Document Revision History for the Agilex 7 FPGAs and SoCs Device Data Sheet: F-Series and I-Series
Electrical Characteristics x
Operating Conditions
Operating Conditions x
Absolute Maximum Ratings Maximum Allowed Overshoot and Undershoot Voltage Recommended Operating Conditions DC Characteristics I/O Standard Specifications
Recommended Operating Conditions x
Recommended Operating Conditions E-Tile Transceiver Power Supply Recommended Operating Conditions P-Tile Transceiver Power Supply Recommended Operating Conditions R-Tile Transceiver Power Supply Recommended Operating Conditions F-Tile Transceiver Power Supply Recommended Operating Conditions HPS Power Supply Recommended Operating Conditions
DC Characteristics x
Supply Current and Power Consumption I/O Pin Leakage Current Bus Hold Specifications OCT Calibration Accuracy Specifications OCT Without Calibration Resistance Tolerance Specifications Pin Capacitance Internal Weak Pull-Up Resistor Hysteresis Specifications for Schmitt Trigger Input
I/O Standard Specifications x
Single-Ended I/O Standards Specifications Single-Ended SSTL, HSTL, HSUL, and POD I/O Reference Voltage Specifications Single-Ended SSTL, HSTL, HSUL, and POD I/O Standards Signal Specifications Differential SSTL, HSTL, and HSUL I/O Standards Specifications Differential POD I/O Standards Specifications Differential I/O Standards Specifications
Switching Characteristics x
Core Performance Specifications Periphery Performance Specifications E-Tile Transceiver Performance Specifications P-Tile Transceiver Performance Specifications R-Tile Transceiver Performance Specifications F-Tile Transceiver Performance Specifications HPS Performance Specifications
Core Performance Specifications x
Clock Tree Specifications I/O PLL Specifications DSP Block Specifications Memory Block Specifications Local Temperature Sensor Specifications Remote Temperature Diode Specifications Voltage Sensor Specifications
Periphery Performance Specifications x
LVDS SERDES Specifications DPA Lock Time Specifications LVDS SERDES Soft-CDR Sinusoidal Jitter Tolerance Specifications Memory Standards Supported DLL Range Specifications Memory Output Clock Jitter Specifications
E-Tile Transceiver Performance Specifications x
E-Tile Transceiver Performance E-Tile Transceiver Reference Clock Specifications E-Tile Transmitter Specifications E-Tile Receiver Specifications
P-Tile Transceiver Performance Specifications x
P-Tile Transceiver Performance P-Tile Transceiver Reference Clock Specifications P-Tile Transmitter Specifications P-Tile Receiver Specifications
R-Tile Transceiver Performance Specifications x
R-Tile Transceiver Performance R-Tile Transceiver Reference Clock Specifications R-Tile Transmitter Specifications R-Tile Receiver Specifications
F-Tile Transceiver Performance Specifications x
F-Tile Transceiver Performance F-Tile Transceiver Reference Clock Specifications F-Tile Transmitter Specifications F-Tile Receiver Specifications F-Tile Electrical Compliance
HPS Performance Specifications x
HPS Clock Performance HPS Internal Oscillator Frequency HPS PLL Specifications HPS Cold Reset HPS SPI Timing Characteristics HPS SD/MMC Timing Characteristics HPS USB UPLI Timing Characteristics HPS Ethernet Media Access Controller (EMAC) Timing Characteristics HPS I2C Timing Characteristics HPS NAND Timing Characteristics HPS Trace Timing Characteristics HPS GPIO Interface HPS JTAG Timing Characteristics HPS Programmable I/O Timing Characteristics
Configuration Specifications x
General Configuration Timing Specifications POR Specifications External Configuration Clock Source Requirements JTAG Configuration Timing AS Configuration Timing Avalon® Streaming (Avalon®-ST) Configuration Timing Configuration Bit Stream Sizes
Agilex™ 7 FPGAs and SoCs Device Data Sheet: F-Series and I-Series

I/O PLL Specifications

Table 30.  I/O PLL Specifications For specification status, see the Data Sheet Status table
Symbol Parameter Condition Min Typ Max Unit
fIN Input clock frequency –1V 10 — 1,10032 MHz
–2V 10 — 90032 MHz
–3V, –3E 10 — 75032 MHz
–4F, –4X 10 — 65032 MHz
fINPFD Input clock frequency to the PFD — 10 — 325 MHz
fVCO I/O PLL VCO operating range –1V 600 — 1,600 MHz
–2V 600 — 1,434 MHz
–3V, –3E 600 — 1,250 MHz
–4F, –4X 600 — 1,067 MHz
fCLBW I/O PLL closed-loop bandwidth I/O bank I/O PLL 0.5 — 10 MHz
Fabric-feeding I/O PLL 1 — 10 MHz
tEINDUTY Input clock or external feedback clock input duty cycle — 40 — 60 %
fOUT Output frequency for internal clock (C counter) –1V — — 1,100 MHz
–2V — — 900 MHz
–3V, –3E — — 750 MHz
–4F, –4X — — 650 MHz
fOUT_EXT Output frequency for external clock output –1V — — 800 MHz
–2V — — 717 MHz
–3V, –3E — — 625 MHz
–4F, –4X — — 500 MHz
tOUTDUTY Duty cycle for dedicated external clock output (when set to 50%) fOUT_EXT < 300 MHz 45 50 55 %
fOUT_EXT ≥ 300 MHz 40/45 33 50 55 33/60 %
tFCOMP 34 External feedback clock compensation time — — — 5 ns
fDYCONFIGCLK Dynamic configuration clock for mgmt_clk — — — 100 MHz
tLOCK Time required to lock from end-of-device configuration or deassertion of areset — — — 1 ms
tDLOCK Time required to lock dynamically (after switchover or reconfiguring any non-post-scale counters/delays) — — — 1 ms
tPLL_PSERR Accuracy of PLL phase shift — — — ±50 ps
tARESET Minimum pulse width on the areset signal — 10 — — ns
tINCCJ Input clock cycle-to-cyle jitter fREF < 100 MHz 35 — — 750 ps (p-p)
fREF ≥ 100 MHz 35 — — 0.15 UI (p-p)
tREFPJ Reference phase jitter (rms)36 Carrier frequency: 100 MHz with integrated bandwidth of 10 kHz to 50 MHz — — 1.42 ps
tREFPN Reference phase noise37 36 10 Hz — — –90 dBc/Hz
100 Hz — — –100 dBc/Hz
1 kHz — — –110 dBc/Hz
10 kHz — — –120 dBc/Hz
100 kHz — — –130 dBc/Hz
1 MHz — — –138 dBc/Hz
10 MHz — — –142 dBc/Hz
100 MHz — — –144 dBc/Hz
tOUTPJ_DC 34 38 Period jitter for dedicated clock output fOUT < 100 MHz 35 — — 17.5 mUI (p-p)
fOUT ≥ 100 MHz 35 — — 175 ps (p-p)
tOUTCCJ_DC 34 38 Cycle-to-cycle jitter for dedicated clock output fOUT < 100 MHz 35 — — 17.5 mUI (p-p)
fOUT ≥ 100 MHz 35 — — 175 ps (p-p)
tOUTPJ_IO 39 38 Period jitter for clock output on the regular I/O fOUT < 100 MHz 35 — — 60 mUI (p-p)
fOUT ≥ 100 MHz 35 — — 600 ps (p-p)
tOUTCCJ_IO 39 38 Cycle-to-cycle jitter for clock output on the regular I/O fOUT < 100 MHz 35 — — 60 mUI (p-p)
fOUT ≥ 100 MHz 35 — — 600 ps (p-p)
tCASC_OUTPJ_DC 34 Period jitter for dedicated clock output in cascaded PLLs fOUT < 100 MHz 35 — — 17.5 mUI (p-p)
fOUT ≥ 100 MHz 35 — — 175 ps (p-p)
Related Information
32 This specification is limited by the I/O maximum frequency. The maximum achievable I/O frequency is different for each I/O standard and is dependent on design and system specific factors. Ensure proper timing closure in your design and perform HSPICE/IBIS simulations based on your specific design and system setup to determine the maximum achievable frequency in your system.
33 To achieve 5% duty cycle for fOUT_EXT ≥ 300 MHz, you only can use tx_outclk port from the LVDS SERDES Intel® FPGA IP. Refer to the related information for the detail design guidelines.
34 Not applicable for fabric-feeding I/O PLL.
35 fREF is fIN/N, specification applies when N = 1.
36 Requirement for Advanced Interface Bus (AIB), High Bandwidth Memory (HBM) Interface, Mobile Industry Processor Interface (MIPI), DDR4 protocol, and LVDS applications only.
37 The phase noise numbers in the table above are the maximum acceptable phase noise values measured at a carrier frequency of 100 MHz. To calculate the phase noise requirement at any other frequency, use the formula: REFCLK phase noise at f (MHz) = REFCLK phase noise at 100 MHz + (20 × log10 (f/100)).
38 This jitter specification does not include the effect of spread-spectrum clock. The magnitude of jitter deterioration is largely depend on the spread-spectrum clock profile used. Refer to the related information for the recommended spread-spectrum clock profile.
39 External memory interface clock output jitter specifications use a different measurement method, which are available in the Memory Output Clock Jitter Specifications table.
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