Intel® Agilex™ 7 FPGAs and SoCs Device Data Sheet: F-Series and I-Series

ID 683301
Date 2/20/2023
Public
Document Table of Contents

Memory Block Specifications

To achieve the maximum memory block performance, use a memory block clock that comes through global clock routing from an on-chip PLL and set to 50% output duty cycle. Use the Intel® Quartus® Prime software to report timing for the memory block clocking schemes.

When you use the error detection cyclical redundancy check (CRC) feature, there is no degradation in fMAX.

Table 32.  Memory Block Performance Specifications For specification status, see the Data Sheet Status table
Memory Mode Performance Unit
–1V –2V –3V, –3E –4F, –4X
MLAB Single-port RAM/ROM

Simple dual-port RAM

1,000 782 667 600 MHz
Simple dual-port RAM with read-during-write option 630 510 460 330 MHz
M20K Block40 Single-port RAM/ROM

Simple dual-port RAM

1,000 (HS)

850 (LP)

782 (HS)

664 (LP)

667 (HS)

567 (LP)

600 (HS)

510 (LP)

MHz
Simple dual-port RAM, coherent read enabled 1,000 (HS)

850 (LP)

782 (HS)

664 (LP)

667 (HS)

567 (LP)

600 (HS)

510 (LP)

MHz
Single-port RAM with the read-during-write option set to Old Data

Simple dual-port RAM with the read-during-write option set to Old Data

800 (HS)

680 (LP)

640 (HS)

540 (LP)

560 (HS)

476 (LP)

480 (HS)

410 (LP)

MHz
Simple dual-port RAM with ECC enabled, 512 × 32 600 (HS)

500 (LP)

480 (HS)

400 (LP)

420 (HS)

357 (LP)

360 (HS)

300 (LP)

MHz
Simple dual-port RAM with ECC, optional pipeline registers enabled, 512 × 32 1,000 (HS)

850 (LP)

782 (HS)

664 (LP)

667 (HS)

567 (LP)

600 (HS)

510 (LP)

MHz
Dual-port ROM

True dual-port RAM

600 (HS) 500 (HS) 420 (HS) 360 (HS) MHz
Simple quad-port RAM 600 (HS) 480 (HS) 420 (HS) 360 (HS) MHz
eSRAM Simple dual-port 750 640 500 500 MHz
40 For M20K block, timing/power optimization feature is available. The available options are High Speed (HS) and Low Power (LP). For details on this timing/power optimization feature, refer to the related information.

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