Agilex™ 7 FPGAs and SoCs Device Data Sheet: F-Series and I-Series

ID 683301
Date 7/08/2024
Public
Document Table of Contents

Differential SSTL, HSTL, and HSUL I/O Standards Specifications

Table 26.  Differential SSTL, HSTL, and HSUL I/O Standards Specifications (for GPIO Bank) For specification status, see the Data Sheet Status table
I/O Standard VCCIO_PIO (V) VILdiff(DC) (V) VIHdiff(DC) (V) VILdiff(AC) (V) VIHdiff(AC) (V) VIX(AC) (V) VOX(AC) (V)
Min Typ Max Max Min Max Min Min Typ Max Min Typ Max
SSTL-12 1.14 1.2 1.26 –0.15 0.15 –0.2 0.2 0.5 × VCCIO_PIO – 0.12 0.5 × VCCIO_PIO 0.5 × VCCIO_PIO + 0.12 0.5 × VCCIO_PIO – 0.12 0.5 × VCCIO_PIO 0.5 × VCCIO_PIO + 0.12
HSTL-12 1.14 1.2 1.26 –0.16 0.16 –0.3 0.3 0.5 × VCCIO_PIO – 0.12 0.5 × VCCIO_PIO 0.5 × VCCIO_PIO + 0.12 0.5 × VCCIO_PIO – 0.12 0.5 × VCCIO_PIO 0.5 × VCCIO_PIO + 0.12
HSUL-12 1.14 1.2 1.26 –0.2 0.2 –0.27 0.27 0.5 × VCCIO_PIO – 0.12 0.5 × VCCIO_PIO 0.5 × VCCIO_PIO + 0.12 0.5 × VCCIO_PIO – 0.12 0.5 × VCCIO_PIO 0.5 × VCCIO_PIO + 0.12