Agilex™ 7 FPGAs and SoCs Device Data Sheet: F-Series and I-Series

ID 683301
Date 7/08/2024
Public
Document Table of Contents

Single-Ended SSTL, HSTL, HSUL, and POD I/O Standards Signal Specifications

Table 25.  Single-Ended SSTL, HSTL, HSUL, and POD I/O Standards Signal Specifications (for GPIO Bank) For specification status, see the Data Sheet Status table
I/O Standard VIL(DC)  (V) VIH(DC) (V) VIL(AC) (V) VIH(AC) (V)
Max Min Max Min
SSTL-12 VREF – 0.075 VREF + 0.075 VREF – 0.100 VREF + 0.100
HSTL-12 VREF – 0.080 VREF + 0.080 VREF – 0.150 VREF + 0.150
HSUL-12 VREF – 0.100 VREF + 0.100 VREF – 0.135 VREF + 0.135
POD1226 VREF – 0.055 VREF + 0.055 VREF – 0.070 VREF + 0.070
Note: For output voltage swing calculation example, refer to the related information.
26 This specification is defined over internal Vref range from 0.6 × VCCIO_PIO to 0.92 × VCCIO_PIO.