Intel Agilex® 7 FPGAs and SoCs Device Data Sheet: F-Series and I-Series

ID 683301
Date 12/04/2023
Public
Document Table of Contents
Give Feedback

Internal Weak Pull-Up Resistor

All I/O pins in GPIO bank have an option to enable weak pull-up when using 1.2 V LVCMOS I/O standard. For SDM and HPS, the configuration I/O and peripheral I/O are supported with weak pull-up and weak pull-down options.

Table 19.  Internal Weak Pull-Up Resistor Values (for GPIO Bank) For specification status, see the Data Sheet Status table
Symbol Description Condition (V) Min Typ Max Unit
RPU Value of the I/O pin pull-up resistor before and during configuration, as well as user mode if you have enabled the programmable pull-up resistor option. VCCIO_PIO = 1.2 ±5% 0.5 2.5 15
Table 20.  Internal Weak Pull-Up and Weak Pull-Down Resistor Values (for HPS and SDM I/O Banks) For specification status, see the Data Sheet Status table
Symbol Description Condition (V) Min Typ Max Unit
20 kΩ RPU, 20 kΩ RPD Value of the I/O pin pull-up and pull-down resistor during user mode if you have enabled the programmable pull-up or pull-down resistor option. VCCIO_SDM = 1.8 ±5%, VCCIO_HPS = 1.8 ±5% 15 20 25
50 kΩ RPU, 50 kΩ RPD Value of the I/O pin pull-up and pull-down resistor during user mode if you have enabled the programmable pull-up or pull-down resistor option. VCCIO_SDM = 1.8 ±5%, VCCIO_HPS = 1.8 ±5% 37.5 50 62.5
80 kΩ RPU, 80 kΩ RPD Value of the I/O pin pull-up and pull-down resistor during user mode if you have enabled the programmable pull-up or pull-down resistor option. VCCIO_SDM = 1.8 ±5%, VCCIO_HPS = 1.8 ±5% 60 80 100