Intel Agilex® 7 FPGAs and SoCs Device Data Sheet: F-Series and I-Series

ID 683301
Date 12/04/2023
Public
Document Table of Contents
Give Feedback

Differential I/O Standards Specifications

Table 28.  Differential I/O Standards Specifications (for GPIO Bank) For specification status, see the Data Sheet Status table
I/O Standard VCCIO_PIO (V) VID (mV) VICM(DC) (V) VOD (V)28 29 VOCM (V)28
Min Typ Max Min Max Min Condition Max Min Typ Max Min Typ Max
True Differential Signaling (Transmitter & Receiver)30 1.455 1.5 1.545 200 600 0.3 Data rate ≤700 Mbps <0.9 0.247 0.454 0.99 1.1 1.21
100 600 0.9 1.4
100 600 0.9 Data rate >700 Mbps 1.4
True Differential Signaling (Receiver only)30 1.14 1.2 1.26 200 600 0.3 Data rate ≤700 Mbps <0.9
100 600 0.9 1.1
100 600 0.9 Data rate >700 Mbps 1.1
28 RL range: 90 ≤ RL ≤ 110 Ω.
29 The specification is only applicable to default VOD and pre-emphasis setting.
30 The True Differential Signaling input buffer is supported on 1.2 V and 1.5 V VCCIO_PIO bank. The maximum input voltage driven into the True Differential Signaling input buffer must not exceed VICM(max) + VID(max)/2.