Intel Agilex® 7 FPGAs and SoCs Device Data Sheet: F-Series and I-Series

ID 683301
Date 12/04/2023
Public
Document Table of Contents
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R-Tile Receiver Specifications

Table 61.  R-Tile Receiver Specifications For specification status, see the Data Sheet Status table
Symbol/Description Condition All Transceiver Speed Grades Unit
Min Typ Max
Supported I/O standards PCIe* High-Speed Differential I/O
CXL High-Speed Differential I/O
Peak-to-peak differential input voltage VID (diff p-p) PCIe* 2.5 GT/s80 175 1,200 mVPP
PCIe* 5.0 GT/s80 100 1,200 mVPP
PCIe* 8.0 GT/s80 25 1,200 mVPP
PCIe* 16.0 GT/s80 15 800 mVPP
PCIe* 32.0 GT/s80 15 800 mVPP
CXL 8.0 GT/s80 25 1,200 mVPP
CXL 16.0 GT/s80 15 800 mVPP
CXL 32.0 GT/s80 15 800 mVPP
Differential on-chip termination resistors PCIe* 80 100 120
CXL 80 100 120
RCOMP PCIe* 81 148.5 150 151.5
CXL81 148.5 150 151.5
80 For PCIe* at 2.5 GT/s and 5 GT/s, VID is measured at TP2, which is the accessible test point at the device under test. For PCIe* and CXL 8.0 GT/s, 16.0 GT/s and 32.0 GT/s, VID is measured at TP2P. TP2P defines a reference point that comprehends the effects of the behavioral Rx package plus Rx equalization and represents the only location where a meaningful eye height and eye width limits can be defined.
81 Connecting RCOMP at 150 Ω calibrates PCIe* and CXL channel on-chip termination to 100 Ω.