Agilex™ 7 FPGAs and SoCs Device Data Sheet: F-Series and I-Series

ID 683301
Date 4/01/2024
Document Table of Contents

P-Tile Transceiver Reference Clock Specifications

Table 53.  P-Tile Reference Clock Specifications For specification status, see the Data Sheet Status table
Symbol/Description Condition All Transceiver Speed Grades Unit
Min Typ Max
Supported I/O standards HCSL
Input reference clock frequency68 99.97 100 100.03 MHz
Rising edge rate69 PCIe* 0.6 4 V/ns
Falling edge rate69 PCIe* 0.6 4 V/ns
Duty cycle PCIe* 40 60 %
Spread-spectrum modulating clock frequency 30 33 kHz
Spread-spectrum downspread –0.5 0 %
Absolute VMAX 1.15 V
Absolute VMIN –0.3 V
Peak-to-peak differential input voltage 300 1,500 mV
VICM (DC coupled) HCSL I/O standard for PCIe* reference clock 250 550 mV
Cycle to cycle jitter (TCCJITTER)70 PCIe* 150 ps
TSSC-MAX-PERIOD-SLEW Max SSC df/dt 1,250 ppm/μs
68 This number is with spread spectrum clocking (SSC) turned off. For systems with spread spectrum clocking, follow the specifications in Section 8.6.3 Data Rate Independent Refclk Parameters in the PCI Express* Base Specification Revision 4.0.
69 Measured from –150 mV to +150 mV on the differential waveform. The 300 mV measurement window is centered on the differential zero crossing.
70 For common reference clock architecture, follow the jitter limit specified in the PCI Express** Card Electromechanical Specification for 2.5 GT/s, Section 4.3.7 Refclk Specifications for 5.0 GT/s and Section 4.3.8 Refclk Specifications for 8.0 GT/s in the PCI Express* Base Specification Revision 3.0, and Section 8.6 Refclk Specifications for 16.0 GT/s in the PCI Express* Base Specification Revision 4.0.