Visible to Intel only — GUID: usx1583213645441
Ixiasoft
Recommended Operating Conditions
E-Tile Transceiver Power Supply Recommended Operating Conditions
P-Tile Transceiver Power Supply Recommended Operating Conditions
R-Tile Transceiver Power Supply Recommended Operating Conditions
F-Tile Transceiver Power Supply Recommended Operating Conditions
HPS Power Supply Recommended Operating Conditions
Single-Ended I/O Standards Specifications
Single-Ended SSTL, HSTL, HSUL, and POD I/O Reference Voltage Specifications
Single-Ended SSTL, HSTL, HSUL, and POD I/O Standards Signal Specifications
Differential SSTL, HSTL, and HSUL I/O Standards Specifications
Differential POD I/O Standards Specifications
Differential I/O Standards Specifications
HPS Clock Performance
HPS Internal Oscillator Frequency
HPS PLL Specifications
HPS Cold Reset
HPS SPI Timing Characteristics
HPS SD/MMC Timing Characteristics
HPS USB UPLI Timing Characteristics
HPS Ethernet Media Access Controller (EMAC) Timing Characteristics
HPS I2C Timing Characteristics
HPS NAND Timing Characteristics
HPS Trace Timing Characteristics
HPS GPIO Interface
HPS JTAG Timing Characteristics
HPS Programmable I/O Timing Characteristics
Visible to Intel only — GUID: usx1583213645441
Ixiasoft
HPS JTAG Timing Characteristics
Symbol | Description | Min | Typ | Max | Unit |
---|---|---|---|---|---|
tJCP | TCK clock period | 41.66 | — | — | ns |
tJCH | TCK clock high time | 20 | — | — | ns |
tJCL | TCK clock low time | 20 | — | — | ns |
tJPSU (TDI) | TDI JTAG port setup time | 5 | — | — | ns |
tJPSU (TMS) | TMS JTAG port setup time | 5 | — | — | ns |
tJPH | JTAG port hold time | 0.5 | — | — | ns |
tJPCO | JTAG port clock to output | 0 | — | 8 | ns |
tJPZX | JTAG port high impedance to valid output | — | — | 10 | ns |
tJPXZ | JTAG port valid output to high impedance | — | — | 10 | ns |
Figure 24. HPS JTAG Timing Diagram
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