Intel® Agilex™ 7 FPGAs and SoCs Device Data Sheet: F-Series and I-Series

ID 683301
Date 2/20/2023
Document Table of Contents

HPS JTAG Timing Characteristics

Table 92.  HPS JTAG Timing Requirements For specification status, see the Data Sheet Status table
Symbol Description Min Typ Max Unit
tJCP TCK clock period 41.66 ns
tJCH TCK clock high time 20 ns
tJCL TCK clock low time 20 ns
tJPSU (TDI) TDI JTAG port setup time 5 ns
tJPSU (TMS) TMS JTAG port setup time 5 ns
tJPH JTAG port hold time 0.5 ns
tJPCO JTAG port clock to output 0 8 ns
tJPZX JTAG port high impedance to valid output 10 ns
tJPXZ JTAG port valid output to high impedance 10 ns
Figure 24. HPS JTAG Timing Diagram

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