Agilex™ 7 FPGAs and SoCs Device Data Sheet: F-Series and I-Series

Download PDF
ID 683301
Date 12/06/2024
Public
Document Table of Contents
Document Table of Contents x
Agilex™ 7 FPGAs and SoCs Device Data Sheet: F-Series and I-Series
Agilex™ 7 FPGAs and SoCs Device Data Sheet: F-Series and I-Series x
Electrical Characteristics Switching Characteristics Configuration Specifications I/O Timing Programmable IOE Delay Glossary Document Revision History for the Agilex 7 FPGAs and SoCs Device Data Sheet: F-Series and I-Series
Electrical Characteristics x
Operating Conditions
Operating Conditions x
Absolute Maximum Ratings Maximum Allowed Overshoot and Undershoot Voltage Recommended Operating Conditions DC Characteristics I/O Standard Specifications
Recommended Operating Conditions x
Recommended Operating Conditions E-Tile Transceiver Power Supply Recommended Operating Conditions P-Tile Transceiver Power Supply Recommended Operating Conditions R-Tile Transceiver Power Supply Recommended Operating Conditions F-Tile Transceiver Power Supply Recommended Operating Conditions HPS Power Supply Recommended Operating Conditions
DC Characteristics x
Supply Current and Power Consumption I/O Pin Leakage Current Bus Hold Specifications OCT Calibration Accuracy Specifications OCT Without Calibration Resistance Tolerance Specifications Pin Capacitance Internal Weak Pull-Up Resistor Hysteresis Specifications for Schmitt Trigger Input
I/O Standard Specifications x
Single-Ended I/O Standards Specifications Single-Ended SSTL, HSTL, HSUL, and POD I/O Reference Voltage Specifications Single-Ended SSTL, HSTL, HSUL, and POD I/O Standards Signal Specifications Differential SSTL, HSTL, and HSUL I/O Standards Specifications Differential POD I/O Standards Specifications Differential I/O Standards Specifications
Switching Characteristics x
Core Performance Specifications Periphery Performance Specifications E-Tile Transceiver Performance Specifications P-Tile Transceiver Performance Specifications R-Tile Transceiver Performance Specifications F-Tile Transceiver Performance Specifications HPS Performance Specifications
Core Performance Specifications x
Clock Tree Specifications I/O PLL Specifications DSP Block Specifications Memory Block Specifications Local Temperature Sensor Specifications Remote Temperature Diode Specifications Voltage Sensor Specifications
Periphery Performance Specifications x
LVDS SERDES Specifications DPA Lock Time Specifications LVDS SERDES Soft-CDR Sinusoidal Jitter Tolerance Specifications Memory Standards Supported DLL Range Specifications Memory Output Clock Jitter Specifications
E-Tile Transceiver Performance Specifications x
E-Tile Transceiver Performance E-Tile Transceiver Reference Clock Specifications E-Tile Transmitter Specifications E-Tile Receiver Specifications
P-Tile Transceiver Performance Specifications x
P-Tile Transceiver Performance P-Tile Transceiver Reference Clock Specifications P-Tile Transmitter Specifications P-Tile Receiver Specifications
R-Tile Transceiver Performance Specifications x
R-Tile Transceiver Performance R-Tile Transceiver Reference Clock Specifications R-Tile Transmitter Specifications R-Tile Receiver Specifications
F-Tile Transceiver Performance Specifications x
F-Tile Transceiver Performance F-Tile Transceiver Reference Clock Specifications F-Tile Transmitter Specifications F-Tile Receiver Specifications F-Tile Electrical Compliance
HPS Performance Specifications x
HPS Clock Performance HPS Internal Oscillator Frequency HPS PLL Specifications HPS Cold Reset HPS SPI Timing Characteristics HPS SD/MMC Timing Characteristics HPS USB UPLI Timing Characteristics HPS Ethernet Media Access Controller (EMAC) Timing Characteristics HPS I2C Timing Characteristics HPS NAND Timing Characteristics HPS Trace Timing Characteristics HPS GPIO Interface HPS JTAG Timing Characteristics HPS Programmable I/O Timing Characteristics
Configuration Specifications x
General Configuration Timing Specifications POR Specifications External Configuration Clock Source Requirements JTAG Configuration Timing AS Configuration Timing Avalon® Streaming (Avalon®-ST) Configuration Timing Configuration Bit Stream Sizes
Agilex™ 7 FPGAs and SoCs Device Data Sheet: F-Series and I-Series

DSP Block Specifications

Table 31.  DSP Block Performance Specifications For specification status, see the Data Sheet Status table
Mode Performance Unit
–1V –2V –3V, –3E –4F, –4X
Fixed-point 18 × 19 multiplication mode 900 771 676 600 MHz
Fixed-point 27 × 27 multiplication mode39 900 771 676 600 MHz
Fixed-point 18 × 19 multiplier adder mode39 900 771 676 600 MHz
Fixed-point 18 × 19 multiplier adder summed with 36-bit input mode39 900 771 676 600 MHz
Fixed-point four 9 × 9 multiplier adder mode39 900 771 676 600 MHz
Fixed-point 18 × 19 systolic mode 900 771 676 600 MHz
Fixed-point 18 × 19 complex multiplication mode 900 771 676 600 MHz
FP32 floating-point multiplication mode 750 579 507 475 MHz
FP32 floating-point adder or subtract mode 750 579 507 475 MHz
FP32 floating-point multiplier adder or subtract mode 750 579 507 475 MHz
FP32 floating-point multiplier accumulate mode 750 579 507 475 MHz
Addition or subtraction of two FP16 floating-point multiplication mode 750 579 507 475 MHz
Sum/sub of two FP16 multiplications with FP32 (addition/subtraction) 750 579 507 475 MHz
Sum/sub of two FP16 multiplications with accumulation (addition/subtraction) 750 579 507 475 MHz
FP32 floating-point complex multiplication 750 579 507 475 MHz
FP32 floating-point vector dot product 750 579 507 475 MHz
FP16 floating-point complex multiplication 750 579 507 475 MHz
FP16 floating-point vector dot product 750 579 507 475 MHz
39 When Chainout is enabled but systolic registers are not used, the performance specifications for the following speed grades are as follows:
  • –1V: 675 MHz
  • –2V: 578 MHz
  • –3V and –3E: 507 MHz
  • –4F and –4X: 450 MHz
Level Two Title