Intel® Agilex™ 7 FPGAs and SoCs Device Data Sheet: F-Series and I-Series

ID 683301
Date 2/20/2023
Document Table of Contents

JTAG Configuration Timing

Table 98.  JTAG Timing Parameters and Values For specification status, see the Data Sheet Status table
Symbol Description Requirement Unit
Minimum Maximum
tJCP TCK clock period 30 ns
tJCH TCK clock high time 14 ns
tJCL TCK clock low time 14 ns
tJPSU (TDI) 120 TDI JTAG port setup time 2 ns
tJPSU (TMS) 120 TMS JTAG port setup time 3 ns
tJPH 120 JTAG port hold time 5 ns
tJPCO JTAG port clock to output 7121 ns
tJPZX JTAG port high impedance to valid output 14 ns
tJPXZ JTAG port valid output to high impedance 14 ns
Figure 26. JTAG Timing Diagram
120 For boundary-scan testing, the TMS and TDI JTAG ports minimum setup time and hold time are 7 ns.
121 Capacitance loading at 10 pF.

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