Intel® Agilex™ 7 FPGAs and SoCs Device Data Sheet: F-Series and I-Series

ID 683301
Date 2/20/2023
Document Table of Contents

General Configuration Timing Specifications

Table 95.  General Configuration Timing Specifications For specification status, see the Data Sheet Status table
Symbol Description Requirement Unit
Min Max
tCF12ST1 nCONFIG high to nSTATUS high 20 ms
tCF02ST0 nCONFIG low to nSTATUS low 400 ms
tST0 nSTATUS low pulse during configuration error 0.5 10 ms
tCD2UM 118 CONF_DONE high to user mode 5 ms
tST12CF0 Minimum time to drive nCONFIG from high to low after nSTATUS transitions from low to high 0 ms
tST02CF1 Minimum time to drive nCONFIG from low to high after nSTATUS transitions from high to low 0 ms
Figure 25. General Configuration Timing Diagram
118 This specification is the initialization time that indicates the time from CONF_DONE signal goes high to INIT_DONE signal goes high.

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