Agilex™ 7 FPGAs and SoCs Device Data Sheet: F-Series and I-Series

ID 683301
Date 7/08/2024
Public
Document Table of Contents

I/O Pin Leakage Current

Table 13.  I/O Pin Leakage Current (for GPIO Bank) For specification status, see the Data Sheet Status table
Symbol Description Condition Min Max Unit
II Input pin VI = 0 V to VCCIO_PIO (MAX) –360 360 µA
IOZ Tri-stated I/O pin VO = 0 V to VCCIO_PIO (MAX) –360 360 µA
Table 14.  I/O Pin Leakage Current (for HPS and SDM I/O Banks) For specification status, see the Data Sheet Status table
Symbol Description Condition Min Max Unit
II Input or tri-stated I/O pin VI, VO = 0 V 0.015 6 µA
VI, VO = VCCIO_HPS (MAX), VCCIO_SDM (MAX) 0.01 1 µA