Intel Agilex® 7 FPGAs and SoCs Device Data Sheet: F-Series and I-Series

ID 683301
Date 12/04/2023
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F-Tile Transmitter Specifications

Table 68.  F-Tile FHT Transmitter Electrical Specifications For specification status, see the Data Sheet Status table
Parameter Symbol Description Min Typical Max Unit
Output eye specifications VTX-DIFF-PKPK Transmit amplitude (low frequency) 800 1,200 mVdiff-pkpk
VTX-DEEMP_STEP Transmit tap resolution for c(0), c(1), and c(–1) 0.5 5 %
Transmit tap resolution for c(–2) 0.5 2.5 %
TTX-SLEW Rise/fall time 8 ps
Transmitter output voltage VTX-CM OUT Transmitter output common-mode voltage 820 850 880 mV
Transmitter DC impedance ZTX-DIFF-DC Transmitter output differential DC impedance 100 W mode while configured 80 100 120
ZTX-CM-DC Transmitter output common-mode DC impedance 20 25 30
Transmitter return loss ZRL-DIFF-DC Transmitter differential DC return loss 14.5 dB
ZRL-DIFF-NYQ Transmitter differential return loss at Nyquist frequency (FBAUD/2) 8 dB
ZRL-CMN Transmitter common-mode return loss below 10 GHz 6 dB
Electrical idle VTX-IDLE Idle output voltage 50 mVpkpk
VCM-DELTA-SQUELCH Maximum common-mode step entering/exiting squelch mode 100 mV
TTX-IDLE-LATENCY Latency entering/exiting idle (cold boot) 28 ms
Power state cycle (re-establish CM) 5 µs
Table 69.  F-Tile FGT Transmitter Electrical Specifications For specification status, see the Data Sheet Status table
Parameter Symbol Description Min Typical Max Unit
Output eye specifications VTX-DIFF-PKPK Back-porch transmit amplitude 300  1,050 mV
VTX-DEEMP_STEP Transmit tap resolution 2 %
DTX-N+2-DEEMP N+2 precursor tap de-emphasis 0 2.5 dB
DTX-N+1-DEEMP N+1 precursor tap de-emphasis 0 4.5 dB
DTX-N-1-DEEMP N-1 postcursor tap de-emphasis 0 6.5 dB
TTX-SLEW Rise/fall time at 20%–80% 10 20 ps
TTX-DJ Transmit deterministic jitter at 25 Gbps 0.15 UIpkpk
TTX-RJ Transmit total peak-peak random jitter89 0.15 UIpkpk
TTX-TJ Transmit total peak-peak jitter (TTX-TJ = TTX-DDJ + TTX-PJ + TTX-RJ)89 0.28 UIpkpk
Transmitter output voltage VTX-CM OUT Transmitter output common-mode voltage 0.45 0.5 0.55 V
Transmitter DC impedance ZTX-DIFF-DC Transmitter output differential DC impedance 90 Ω mode while configured90 80 90 120
ZTX-CM-DC Transmitter output common-mode DC impedance 20 25 30
Transmitter return loss ZRL-DIFF-DC Transmitter differential DC return loss 12 dB
ZRL-DIFF-NYQ Transmitter differential return loss at Nyquist frequency (FBAUD/2) 6 dB
ZRL-CMN Transmitter common-mode return loss below 10 GHz 6 dB
Electrical idle VTX-IDLE Idle output voltage 20 mV
VCM-DELTA-SQUELCH Maximum common-mode step entering/exiting squelch mode 100 mV
TTX-IDLE-LATENCY Latency entering/exiting idle (cold boot), power state cycle (re-establish CM) 8 µs
Receiver detect VTX-RCV-DETECT Voltage change allowed during receiver detection 600 mV
Lane-to-lane output skew Lane count ≤ 8 2 UI + 200 ps ps
Lane count = 16 2 UI + 300 ps ps
89 Assume a 1st order high-pass jitter measurement filter with a cutoff of Fbaud/Fgpll = Ngpll.
90 TX pins are driven to 0 V before mode configuration.