Intel® Agilex™ 7 FPGAs and SoCs Device Data Sheet: F-Series and I-Series

ID 683301
Date 2/20/2023
Document Table of Contents

E-Tile Receiver Specifications

Table 49.  E-Tile Receiver Specifications For specification status, see the Data Sheet Status table
Symbol/Description Condition Min Typ Max Unit
Absolute VMAX for a receiver pin NRZ VCCH_GXE + 0.3 V
Maximum peak-to-peak differential input voltage VID (diff p-p) before/after device configuration 1.2 V
VCM (Internal AC coupled)63 NRZ GND VCCH_GXE V
PAM4 GND + 0.3 VCCH_GXE – 0.3 V
Receiver run length64 10065 symbols
DC input impedance 40 60
DC differential input impedance 80 100 120
Powered down DC input impedance Receiver pin impedance when the receiver termination is powered down 100k
Differential termination From DC to 100 MHz 80 100 120
PPM tolerance Allowed frequency mismatch between REFCLK and RX data 750 ppm
63 This value uses internal AC coupling. External coupling capacitors are required beyond the range mentioned in this table.
64 No additional transition density requirements apply.
65 The incoming data must be statistically DC-balanced.

Did you find the information on this page useful?

Characters remaining:

Feedback Message